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rev.b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adv7190/adv7191 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 video encoders with six 10-bit dacs and 54 mhz oversampling features six high quality 10-bit video dacs multistandard video input multistandard video output 4 oversampling with internal 54 mhz pll programmable video control includes: digital noise reduction gamma correction luma delay chroma delay multiple luma and chroma filters luma ssaf? (super subalias filter) average brightness detection field counter macrovision rev 7.1 (adv7190 only) cgms (copy generation management system) wss (wide screen signaling) closed captioning support teletext insertion port (pal-wst) 2-wire serial mpu interface supply voltage 5 v and 3.3 v operation 64-lead lqfp package simplified functional block diagram i 2 c interface chroma lpf 10-bit dac 10-bit dac 10-bit dac 10-bit dac 10-bit dac 10-bit dac 2 oversampling 4 oversampling or adv7190/adv7191 ssaf lpf luma lpf composite video y [s-video] c [s-video] rgb yuv tvscreen color control dnr gamma correction vbi teletext closed caption cgms/wss macrovision demux and ycrcb? to? yuv matrix pll and 54mhz video input processing video output processing video signal processing analog output 27mhz clock itu?r.bt 656/601 8-bit ycrcb in 4:2:2 format digital input 1 throughout the document, yuv refers to digital or analog component video. the macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. please contact sales of?e for latest available macrovision version. itu-r and ccir are used interchangeably in this document (itu-r has replaced ccir recommendations). ssaf is a trademark of analog devices inc. i 2 c is a registered trademark of philips corporation. applications dvd playback systems, pc video/multimedia playback systems general description the adv7190/adv7191 is part of the new generation of video encoders from analog devices. the device builds on the perfor- mance of previous video encoders and provides new f eatures such as digital noise reduction, gamma correction, 4 oversam- pling and 54 mhz operation, average brightness detection, chroma delay, an additional chroma filter, and so on. the adv7190/adv7191 supports ntsc-m, ntsc-n ( japan), pal n, pal m, pal-b/d/g/h/i, and pal-60 standards. input stan dards supported include itu-r.bt656/601 4:2:2 ycrcb in 8- or 16-bit format. the adv7190/adv7191 can output composite video (cvbs), s-video (y/c), component yuv 1 , or rgb. the analog component output is also compatible with betacam, mii and smpte/ebu n10 levels, smpte 170m ntsc, and itu- r.bt 470 pal. for more information about the adv7190/adv7191? fea tures, refer to detailed description. continued on page 11
adv7190/adv7191 C2C rev. b contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . 1 specifications 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 v dynamic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 v dynamic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 v timing characteristics . . . . . . . . . . . . . . . . 6 3.3 v timing characteristics . . . . . . . . . . . . . . . . 7 absolute maximum ratings . . . . . . . . . . . . . . . . . 9 package thermal performance . . . . . . . . . . . . . 9 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin function descriptions . . . . . . . . . . . . . . . . . 10 detailed description of features . . . . . . . . . 11 general description . . . . . . . . . . . . . . . . . . . . . . . . 11 data path description . . . . . . . . . . . . . . . . . . . . . 12 internal filter response.. . . . . . . . . . . . . . . . . . . 13 features: functional description . . . . . . . . . 17 brightness detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 chroma/luma delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 clamp output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 cso , hso , and vso outputs . . . . . . . . . . . . . . . . . . . . . 17 color bar generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 color burst signal control . . . . . . . . . . . . . . . . . . . . . . . 17 color controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 chrominance control . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 undershoot limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 d igital noise reduction . . . . . . . . . . . . . . . . . . . . . . . . . . 17 d ouble buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 gamma correction control . . . . . . . . . . . . . . . . . . . . . . . 18 ntsc pedestal control . . . . . . . . . . . . . . . . . . . . . . . . . . 18 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 real-time control, subcarrier reset, and timing reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 sch phase mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 square pixel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 vertical blanking data insertion and blank input . . . . 19 yuv levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 16-bit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 oversampling and internal pll . . . . . . . . . . . . . . . . . 19 video timing description . . . . . . . . . . . . . . . . . . . 19 reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mpu port description . . . . . . . . . . . . . . . . . . . . . . . 27 register accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 register programming . . . . . . . . . . . . . . . . . . . . . 28 mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 timing registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 subcarrier frequency and phase registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 closed captioning registers . . . . . . . . . . . . . . . 36 ntsc pedestal registers . . . . . . . . . . . . . . . . . . . . 37 teletext request control register . . . . . . 37 cgms_wss registers . . . . . . . . . . . . . . . . . . . . . . . . . 37 contrast control register . . . . . . . . . . . . . . . . 38 color control registers . . . . . . . . . . . . . . . . . . 38 hue adjust control register . . . . . . . . . . . . . . 39 brightness control registers . . . . . . . . . . . . . 39 sharpness control register . . . . . . . . . . . . . . . 40 dnr registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 gamma correction registers . . . . . . . . . . . . . . 42 brightness detect register . . . . . . . . . . . . . . . . 43 output clock register . . . . . . . . . . . . . . . . . . . . . 43 appendix 1 board design and layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . 44 appendix 2 closed captioning . . . . . . . . . . . . . . . . . . . . . . . . 46 appendix 3 copy generation management system (cgms) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 appendix 4 wise screen signaling (wss) . . . . . . . . . . . . . . . 48 appendix 5 teletext insertion . . . . . . . . . . . . . . . . . . . . . . . 49 appendix 6 optional output filter . . . . . . . . . . . . . . . . . . 50 appendix 7 dac buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 appendix 8 recommended register values . . . . . . . . . . . 52 appendix 9 ntsc waveforms (with pedestal) . . . . . . . . . 56 ntsc waveforms (without pedestal) . . . . . 57 pal waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 uv waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 output waveforms . . . . . . . . . . . . . . . . . . . . . . . . 60 video measurement plots . . . . . . . . . . . . . . . . 64 appendix 10 vector plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 69 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
?3? rev. b adv7190/adv7191 5 v specifications 1 parameter min typ max unit test conditions static performance resolution (each dac) 10 bits accuracy (each dac) integral nonlinearity 3 1.0 lsb differential nonlinearity 3 1.0 lsb guaranteed monotonic digital inputs input high voltage, v inh 2v input low voltage, v inl 0.8 v input current, i in 0 1 m av in = 0.4 v or 2.4 v input capacitance, c in 610 pf input leakage current 1 m a digital outputs output high voltage, v oh 2.4 v i source = 400 m a output low voltage, v ol 0.8 0.4 v i sink = 3.2 ma three-state leakage current 10 m a three-state output capacitance 6 10 pf analog outputs output current (max) 4.125 4.33 4.625 ma r l = 300 w , r set1,2 = 1200 w output current (min) 2.16 ma r l = 600 w , r set1,2 = 2400 w dac-to-dac matching 3 0.4 2.5 % output compliance, v oc 0 1.4 v output impedance, r out 100 k w output capacitance, c out 6pfi out = 0 ma voltage reference 4 reference range, v ref 1.112 1.235 1.359 v power requirements v aa 4.75 5.0 5.25 v normal power mode i dac 5 29 35 ma i cct (2 oversampling) 6, 7 80 120 ma i cct (4 oversampling) 6, 7 120 170 ma i pll 610 ma sleep mode i dac 0.01 m a i cct 85 m a notes 1 all measurements are made in 4 oversampling mode unless otherwise specited. 2 temperature range t min to t max : 0
?4? rev. b adv7190/adv7191especifications 3.3 v specifications 1 parameter min typ max unit test conditions static performance resolution (each dac) 10 bits accuracy (each dac) integral nonlinearity 1.0 lsb differential nonlinearity 1.0 lsb guaranteed monotonic digital inputs input high voltage, v inh 2v input low voltage, v inl 0.8 v input current, i in 1 m av in = 0.4 v or 2.4 v input capacitance, c in 610 pf input leakage current 1 m a digital outputs output high voltage, v oh 2.4 v i source = 400 m a output low voltage, v ol 0.4 v i sink = 3.2 ma three-state leakage current 10 m a three-state output capacitance 6 10 pf analog outputs output current (max) 4.25 4.33 4.625 ma r set1,2 = 1200 w , r l = 300 w output current (min) 2.16 ma r l = 600 w , r set1,2 = 2400 w dac-to-dac matching 0.4 % output compliance, v oc 1.4 v output impedance, r out 100 k w output capacitance, c out 630 pfi out = 0 ma voltage reference 3 reference range, v ref 1.235 v i vrefout = 20 m a power requirements v aa 3.15 3.3 3.45 v normal power mode i dac 4 29 ma i cct (2 oversampling) 5, 6 42 54 ma i cct (4 oversampling) 5, 6 68 86 ma i pll 6ma sleep mode i dac 0.01 m a i cct 85 m a notes 1 all measurements are made in 4 oversampling mode unless otherwise specited and are guaranteed by characterization. in 2 oversampling mode, the power re- quirement for the adv7190/adv7191 are typically 3.0 v. 2 temperature range t min to t max : 0
?5? rev. b adv7190/adv7191 5 v dynamicespecifications 1 parameter min typ max unit test conditions differential gain 3 0.1 (0.4) 0.3 (0.5) % differential phase 3 0.4 (0.15) 0.5 (0.3) degrees snr (pedestal) 3 78.5 (78) db rms rms 78 (78) db p-p peak periodic snr (ramp) 3 61.7 (61.7) db rms rms 62 (63) db p-p peak periodic hue accuracy 0.5 degrees color saturation accuracy 0.7 % chroma nonlinear gain 0.7 0.9 %r eferenced to 40 ire chroma nonlinear phase 0.5 degrees chroma/luma intermod 0.1 % chroma/luma gain ineq 1.7 % chroma/luma delay ineq 2.2 ns luminance nonlinearity 0.6 0.7 % chroma am noise 82 db chroma pm noise 72 db notes 1 all measurements are made in 4 oversampling mode unless otherwise specited. 2 temperature range t min to t max : 0
adv7190/adv7191 ?6? rev. b 5 v timing characteristics parameter min typ max unit test conditions mpu port 2 sclock frequency 0 400 khz sclock high pulsewidth, t 1 0.6 m s sclock low pulsewidth, t 2 1.3 m s hold time (start condition), t 3 0.6 m s after this period, the first clock is generated setup time (start condition), t 4 0.6 m sr elevant for repeated start condition data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 0.6 m s analog outputs 2 analog output delay 8 ns dac analog output skew 0.1 ns clock control and pixel port 3 f clock 27 mhz clock high time, t 9 8ns clock low time, t 10 8ns data setup time, t 11 6ns data hold time, t 12 5ns control setup time, t 11 6ns control hold time, t 12 4ns digital output access time, t 13 13 ns digital output hold time, t 14 12 ns pipeline delay, t 15 (2 oversampling) 57 c lock cycles pipeline delay, t 15 (4 oversampling) 67 c lock cycles teletext port 4 digital output access time, t 16 11 ns data setup time, t 17 3ns data hold time, t 18 6ns reset control reset lt ll llo h notes tt n t a hsync , vsync , blank , cclkn t ottre, tt s v aa v v,v re v,r set, , a t n t a ,
?7? rev. b adv7190/adv7191 3.3 v timing characteristics parameter min typ max unit test conditions mpu port sclock frequency 0 400 khz sclock high pulsewidth, t 1 0.6 m s sclock low pulsewidth, t 2 1.3 m s hold time (start condition), t 3 0.6 m sa fter this period, the first clock is generated setup time (start condition), t 4 0.6 m sr elevant for repeated start condition data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 0.6 2 m s analog outputs analog output delay 8 ns dac analog output skew 0.1 ns clock control and pixel port 3 f clock 27 mhz clock high time, t 9 8ns clock low time, t 10 8ns data setup time, t 11 6ns data hold time, t 12 4ns control setup time, t 11 2.5 ns control hold time, t 12 3ns digital output access time, t 13 13 ns digital output hold time, t 14 12 ns pipeline delay, t 15 (2 oversampling) 57 c lock cycles pipeline delay, t 15 (4 oversampling) 67 c lock cycles teletext port 4 digital output access time, t 16 11 ns data setup time, t 17 3ns data hold time, t 18 6ns reset control reset lt ll llo h notes tt n t a hsync , vsync , blank , cclkn t ottre, tt s v aa v v,v re v,r set, ,a t n t a ,
adv7190/adv7191 ?8? rev. b t 3 t 2 t 6 t 1 t 7 t 5 t 3 t 4 t 8 sda scl figure 1. mpu port timing diagram t 9 t 11 clock pixel input data t 10 t 12 hsync vsync blank c y c y c y hsync vsync blank cso_hso vso cla control s control os ct ttre clock tt clock cycles clock cycles clock cycles clock cycles clock cycles tt
adv7190/adv7191 ?9? rev. b absolute maximum ratings 1 v aa to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v voltage on any digital input pin . . . . gnd e 0.5 v to v aa + 0.5 v storage temperature (t s ) . . . . . . . . . . . . . . e65 j unction temperature = ( v aa ( i dac + i cct )) q j a + 70 vso cl a cso_hso reset r set v re co aca acb v aa an acc ac an v aa ace ac co r set an an hsync vsync blank alsb ttre an v aa an v aa scl sa scresetrtctr clkn clkot v aa
adv7190/adv7191 ?10? rev. b pin function descriptions pin input/ no. mnemonic output function 1e16 p0ep15 i 8 -bit or 16-bit 4:2:2 multiplexed ycrcb pixel port. the lsb of the input d ata is set up on pin p0. 17, 25, 29, v aa pa nalog power supply (3.3 v to 5 v). 38, 43, 54, 63 18, 24, 26, agnd g analog ground. 33, 39, 42, 55, 64 19 hsync o hsync ,,cst sss vsync o vs ync cst s vsync cs blank o vbcstv b blank alsb ttlatlsb ttre o tros, clkn ttlcrha , hntschal clkot o co scl sc sa o so screset rtcrtc,tr,sr rtctr r set a vsac,e, co o c ac,e,c ccov aa ac o svcvreaot ac a ace o svybleaotaca ac o c yreenaotaca acc o svcvreaotaca acb o svybleaotac a aca o cyreenaot aca co o c aca,b,cc ccov aa v re o vracvrova v re r set a vsaca,b,c reset t avav sar cso_hso o cso hso ossttll vso cla o vso ossttlclattlos vs al_ntsc alntsc,lal , nc nc tt t
adv7190/adv7191 ?11? rev. b i n t e r p o l a t o r modulator and hue control brightness control and add sync and interpolator saturation control and add burst and interpolator programmable luma filter and sharpness filter programmable chroma filter sin/cos dds block real-time control circuit screset/rtc/tr i n t e r p o l a t o r m u l t i p l e x e r yuv-to-rgb matrix and yuv level control block 10-bit dac 10-bit dac 10-bit dac dac control block 10-bit dac 10-bit dac 10-bit dac dac control block dac a dac b dac c v ref r set2 comp2 dac d dac f dac e r set1 comp1 dnr and gamma correction 10 10 10 v u y ycrcb to yuv matrix 10 10 10 v u y pll demux 10 10 10 teletext insertion block video timing generator cgms/wss and closed captioning control i 2 c mpu port alsb sda scl pal_ntsc vso cla cso_hso hsync vsync blank reset tt ttre clkn clkot avav b etaleescrtonoeatres c shcrr ohll so a vc nr hbcs cos vbvb s la chroa c lc lssass ab c no cocvt so cscs ssss ravo ccs talst s crsvsync eneralescrton t avavve ccr sacavav a sv ycv rbvyvvayv bsteebn nr t nr sbtractsnalnthreshol raneroornalsnal lterott threshol lterott threshol ntlter block ansnalath nosesnalath yata nt nrot asnalabovethreshol ranetoornalsnal nrcontrol blocksecontrol borerarea blockoset an cornanata cornanborer nrsharnessoe lterott threshol lterott threshol ntlter block ansnalath nosesnalath yata nt nrot nrcontrol blocksecontrol borerarea blockoset an cornanata cornanborer nroe bnrnrs
adv7190/adv7191 ?12? rev. b programmable gamma correction is also available. figure 6 shows the response of different gamma values to a ramp signal. 250 200 150 100 50 0 300 signal outputs signal input 0.5 gamma correction block output to a ramp input for various gamma values gamma?corrected amplitude 050 100 150 200 250 location 0.3 1.5 1.8 figure 6. signal input (ramp) and selectable gamma output curves t he on-board ssaf (super subalias filter) with extended luminance frequency response and sharp stopband attenuation enables studio quality video playback on modern tvs, giving o ptimal horizontal line resolution. an additional sharpness control feature allows high-frequency enhancement on the lumi- nance signal. the device is driven by a 27 mhz clock. data can be output at 27 mhz or 54 mhz (on-board pll) when 4 oversampling is enabled. also, the output filter requirements in 4 oversam pling and 2 oversampling differ, as can be seen in figure 7. ?30db 0db 6.75mhz 13.5mhz 27.0mhz 40.5mhz 54.0mhz 2 filter requirements 4 filter requirements figure 7. output filter requirements in 4 oversampling mode encoder core 2 i n t e r p o l a t i o n 6 d a c o u t p u t s 54mhz output rate adv7190/adv7191 pll 54mhz mpeg2 pixel bus 27mhz figure 8. pll and 4 oversampling block diagram the adv7190/adv7191 also supports both pal and ntsc square pixel operation. in this case the encoder requires a 2 4.5454 mhz clock for ntsc or 29.5 mhz clock for pal square pixel mode operation. all internal timing is generated on-chip. an advanced power management circuit enables optimal control of power consumption in normal operating modes or sleep modes. the output video frames are synchronized with the incoming data timing reference codes. optionally, the encoder accepts (and can generate) hsync , vsync, el t hso cso vso ttl a tavavsscsa tav r tavav c , avav t avavl ataathescrton alb,,,h,,,n,ntsc,n,ycc ccr ht y,c c , y,c,c t avavalb,,,h,,n nts c , nala v alnr y y ty tc,c a t ,, y cc,avc c,ty h o t r t vs sc t v cstly hc ht
adv7190/adv7191 ?13? rev. b table i. luminance internal filter specitcations (4 oversampling) passband 3 db bandwidth 2 filter type filter selection ripple 1 (db) (mhz) mr04 mr03 mr02 low-pass (ntsc) 0 0 0 0.16 4.24 low-pass (pal) 0 0 1 0.1 4.81 notch (ntsc) 0 1 0 0.09 2.3/4.9/6.6 notch (pal) 0 1 1 0.1 3.1/5.6/6.4 extended (ssaf) 1 0 0 0.04 6.45 cif 1 0 1 0.127 3.02 qcif 1 1 0 monotonic 1.5 notes 1 passband ripple is detned to be fluctuations from the 0 db response in the passband, measured in (db). the passband is detned to have 0-fc frequency limits for a low-pass tlter, 0ef1 and f2eintnity for a notch tlter, where fc, f1, f2 are the e3 db points. 2 3 db bandwidth refers to the e3 db cutoff frequency. table ii. chrominance internal filter specitcations (4 oversampling) passband 3 db bandwidth 2 filter type filter selection ripple 1 (db) (mhz) mr07 mr06 mr05 1.3 mhz low-pass 0 0 0 0.09 1.395 0.65 mhz low-pass 0 0 1 monotonic 0.65 1.0 mhz low-pass 0 1 0 monotonic 1.0 2.0 mhz low-pass 0 1 1 0.048 2.2 3.0 mhz low-pass 1 1 1 monotonic 3.2 cif 1 0 1 monotonic 0.65 qcif 1 1 0 monotonic 0.5 notes 1 passband ripple is detned to be fluctuations from the 0 db response in the passband, measured in (db). the passband is detned to have 0-fc frequency limits for a low-pass tlter, 0ef1 and f2eintnity for a notch tlter, where fc, f1, f2 are the e3 db points. 2 3 db bandwidth refers to the e3 db cutoff frequency. l uma and chroma signals are added together to make up the composite video signal. all timing signals are controlled. the ycrcb data is also used to generate rgb data with appropri- ate sync and blank levels. the yuv levels are scaled to output the suitable smpte/ebu n10, mii, or betacam levels. e ach dac can be individually powered off if not required. a complete description of dac output contgurations is given in the mr2 bit description section. video output levels are illustrated in appendix 9. internal filter response t he y filter supports several different frequency responses including two low-pass responses, two notch responses, an extended (ssaf) response with or without gain boost/attenuation, a cif response and a qcif response. the uv filter supports several different frequency responses including tve low-pass responses, a cif response and a qcif response, as can be seen on the following pages. in extended mode there is the option of twelve responses in the range from e4 db to +4 db. the desired response can be chosen by the user by programming the correct value via the i 2 c. the variation of frequency responses can be seen on the following pages. for more detailed plots refer to an-562 ana log devices? application note.
adv7190/adv7191 ?14? rev. b 0 ?20 0 ?50 ?60 ?30 ?10 24 10 12 68 ?70 ?40 frequency ? mhz magnitude ? db figure 9. ntsc low-pass luma filter 0 ?20 0 ?50 ?60 ?30 ?10 24 10 12 68 ?70 ?40 frequency ? mhz magnitude ? db figure 10. pal low-pass luma filter 0 ?20 0 ?50 ?60 ?30 ?10 24 10 12 68 ?70 ?40 magnitude ? db frequency ? mhz figure 11. extended mode (ssaf) luma filter 0 ?20 0 ?50 ?60 ?30 ?10 24 10 12 68 ?70 ?40 magnitude ? db frequency ? mhz figure 12. ntsc notch luma filter 0 ?20 0 ?50 ?60 ?30 ?10 24 10 12 68 ?70 ?40 magnitude ? db frequency ? mhz figure 13. pal notch luma filter 5 0 0 1 3 4 12 6 7 3 5 ?1 2 magnitude ? db frequency ? mhz 4 figure 14. extended ssaf and programmable gain, showing range 0 db/+4 db range
adv7190/adv7191 ?15? rev. b 1 0 ?4 ?3 ?1 0 12 6 7 3 5 ?5 ?2 magnitude ? db frequency ? mhz 4 figure 15. extended ssaf and programmable attenuation, showing range 0 db/?4 db 4 0 0 ?8 ?6 ?2 2 12 6 7 3 5 ?12 ?4 magnitude ? db frequency ? mhz ?10 4 figure 16. extended ssaf and programmable attenuation, showing range +4 db/?12 db 0 ?20 0 ?50 ?60 ?30 ?10 24 10 12 68 ?70 ?40 magnitude ? db frequency ? mhz figure 17. luma cif filter 0 ?20 0 ?50 ?60 ?30 ?10 24 10 12 68 ?70 ?40 magnitude ? db frequency ? mhz figure 18. qcif filter 0 ?20 0 ?50 ?60 ?30 ?10 24 10 12 68 ?70 ?40 magnitude ? db frequency ? mhz figure 19. chroma 0.65 mhz low-pass filter 0 ?20 0 ?50 ?60 ?30 ?10 24 10 12 68 ?70 ?40 magnitude ? db frequency ? mhz figure 20. chroma 1.0 mhz low-pass filter
adv7190/adv7191 ?16? rev. b 0 ?20 0 ?50 ?60 ?30 ?10 24 10 12 68 ?70 ?40 magnitude ? db frequency ? mhz figure 21. chroma 1.3 mhz low-pass filter 0 ?20 0 ?50 ?60 ?30 ?10 24 10 12 68 ?70 ?40 magnitude ? db frequency ? mhz figure 22. chroma 2 mhz low-pass filter 0 ?20 0 ?50 ?60 ?30 ?10 24 10 12 68 ?70 ?40 magnitude ? db frequency ? mhz figure 23. chroma 3 mhz low-pass filter 0 ?20 0 ?50 ?60 ?30 ?10 24 10 12 68 ?70 ?40 magnitude ? db frequency ? mhz figure 24. chroma cif filter 0 ?20 0 ?50 ?60 ?30 ?10 24 10 12 68 ?70 ?40 magnitude ? db frequency ? mhz figure 25. chroma qcif filter
adv7190/adv7191 ?17? rev. b features: functional description brightness detect t his feature is used to monitor the average brightness of the in coming y signal on a teld-by-teld basis. the information is r ead from the i 2 c and based on this information, the color satu ration, contrast and brightness controls can be ad justed (for example to com pens ate for very dark pictures). (brightness detect register.) chroma/luma delay t he luminance data can be delayed by maximum of six clock cycles. additionally the chroma can be delayed by a maximum of eight clock cycles (one clock cycle at 27 mhz). (timing register 0 and mode register 9.) chroma delay luma delay figure 26. chroma delay figure 27. luma delay clamp output t he adv7190/adv7191 has a programmable clamp ttl output signal. this clamp signal is programmable to the front and back porch. the clamp signal can be varied by one to three clock cycles in a positive and negative direction from the default position. (mode r egister 5, mode register 7.) cvbs output pin clamp output pin mr57 = 1 mr57 = 0 clamp o/p signals figure 28. clamp output timing cso , hso , vso otts e avav sts tee tt t s s, cso css, hso hs s vso vsstttl s r ott veo ealentsc cso hso vso cso hso vso t c tvv tsc r csc t r cc tvv t contrast control contrast adjustment is achieved by scaling the y input data by a factor programmed by the user. this factor allows the data to be scaled between 0% and 150%. (contrast control register.) brightness control the brightness is controlled by adding a programmable setup level onto the scaled y data. f or ntsc with pedestal, the setup can vary from 0 ire to 22.5 ire. for ntsc w ithout pedestal and pal, the setup can vary from e7.5 ire to +15 ire. (brightness control register.) color saturation color adjustment is achieved by scaling the cr and cb input data by a factor programmed by the user. this factor allows the data to be scaled between 0% and 200%. (u scale register and v scale register.) hue adjust control the hue adjustment is achieved on the composite and chroma outputs by adding a phase offset onto the color subcarrier in the a ctive video but leaving the color burst unmodited, i.e., only the phase between the video and the colorburst is modited and thu s the hue is shifted. the adv7190/adv7191 provides a range of 22
adv7190/adv7191 ?18? rev. b in dnr mode, if the absolute value of the tlter output is smaller than the threshold, it is assumed to be noise. a programmable amount (coring gain control) of this noise signal will be sub- tracted from the original signal. in dnr sharpness mode, if the absolute value of the tlter output is less than the programmed threshold, it is assumed to be noise, as before. otherwise, if the level exceeds the threshold, now being identited as a valid signal, a fraction of the signal (coring gain control) will be added to the original signal in order to boost high frequency components and to sharpen the video image. in mpeg systems it is common to process the video information in blocks of 8 8 pixels for mpeg2 systems, or 16 16 pixels for mpeg1 systems (block size control). dnr can be applied to t he resulting block transition areas that are known to contain noise. generally the block transition area contains two pixels. it is possible to detne this area to contain four pixels (border area control). it is also possible to compensate for variable block positioning or d ifferences in ycrcb pixel timing with the use of the (block offset control). see figure 82 for further information. (mode register 8, dnr registers 0e2.) double buffering double buffering can be enabled or disabled on the following registers: closed captioning registers, brightness control, v scale, u scale, contrast control, hue adjust, the gamma curve select bit, and macrovision registers (adv7190 only). these registers are updated once per teld on the falling edge of the vsync avav, , r cc t , aba s crr, cr ntscc ntsc r o reset ate e, t s eess t eete reset a reset t sa reset rtc,sr,tr tscresetrtctrr c,avav tr,sr rtc atnreset o, t h, tsbcarrerhase rtcoe,avav t avav rtc av, t b eh s av r sch tsch ntscal sch,sch ,, t s,sch r sch sch,sch asch av av rtc sr sch tsr,,sch ,s ral sch r s , reset ,scresetrtctrntsc_al ,avav s s ,ss r, cr r s tavav ntsch a,al, h t s or
adv7190/adv7191 ?19? rev. b vertical blanking data insertion and blank t t s sse t e ycc t tse es vb tt t e e s est et ses see es t s e et s e t b t s te set vb t o ee vb t te ee tt e s t s eset te ycc t ste e, ss t, cs, vs et atete, te ete vb e e vb t sete tese es vb s e t es t s sse t t e te blank t r blank tr , blank s,, blank tr , blank av av ccrtr yvl tavav steby alntsc s v b v v ste v v v v a cvbssvyc yycc t v,vv ntscvalr b , hsync vsync blank s seavsav r oll ach o h o tavavh t hll ,h, o llh note o o r,rsa h h ott ll n t e r o l a t o n h a c o t t s encoer avav elbs encoer core e lter rereents lter rereents reencyh ll ob veotnescrton tavav eea, avavycc ccrvt s vtssvt tavav tavav ,, c ,avavalntsc t h ntsc halt tavav stc hsync , blank , vsync t r r, tr, resetseence reset avav a tavav ntsc_al
adv7190/adv7191 ?20? rev. b when reset y, c,c avavo aca,b,c ac,e, ,vc r tr , o taltnsnalssresse tnactve valveo valveo valveo blackvale blackvalethsync reset ac ace ac aca acb acc r el_ata_val taltn reset st tscs cc r rovs s reset
adv7190/adv7191 ?21? rev. b composite video e.g., vcr or cable clock green/composite/y blue/luma/u adv7190/adv7191 p7?p0 screset/rtc/tr video decoder adv7185 gll lcc1 p19?p12 red/chroma/v green/composite/y blue/luma/u red/chroma/v h/l transition count start low 128 rtc time slot: 01 14 67 68 not used in adv7190/ adv7191 19 valid sample invalid sample f sc pll increment 1 8/ line locked clock 5 bits reserved sequence bit 2 reset bit 3 reserved 4 bits reserved 21 0 13 14 bits reserved 0 notes: 1 f sc pll increment is 22 bits long, value loaded into adv7190/adv7191. fsc dds register is f sc pll increments bits 21:0 plus bits 0:9 of subcarrier frequency registers. all zeros should be written to the subcarrier frequency registers of the adv7190/adv7191. 2 sequence bit pal: 0 = line normal, 1 = line inverted ntsc: 0 = no change 3 reset bit reset adv7190/adv7191?s dds figure 32. rtc timing and connections mode 0 (ccire656): slave option (timing register 0 tr0 = x x x x x 0 0 0) the adv7190/adv7191 is controlled by the sav (s tart active video) and eav (end active video) time codes in the pixel data. all tim ing information is transmitted using a 4-byte synchronization pattern. a synchronization pattern is sent immediately before and after each line during active picture and retrace. mode 0 is illu stra ted in figure 33. the hsync , vsync blank y c y y a b a b a b y c y c c y c y c eavcoe savcoe ancllaryata hanc clock clock clock clock clock clock clock clock enoactve veolne startoactve veolne analo veo ntels ntscalsyste lnesh alsyste lnesh y t,s
adv7190/adv7191 ?22? rev. b mode 0 (ccire656): master option (timing register 0 tr0 = x x x x x 0 0 1) t he adv7190/adv7191 gene rates h, v, and f signals required for the sav and eav time codes in the ccir656 standard. the h bit is output on the hsync ,v blank vsync ntscalth,v, slay slay vertcalblank oel evenel h v oel evenel slay slay vertcalblank h v t,ntsc slay slay vertcalblank h v oel evenel slay slay vertcalblank h v oel evenel t,al
adv7190/adv7191 ?23? rev. b analog video h f v figure 36. timing mode 0 data transitions, master mode mode 1: slave option hsync , blank , l reste r ts e te avav ets ht sync o e l ss a tst te l t e h sync ,,vrt blank blank avavccr ntscal oel evenel slay slay vertcalblank hsync blank el slay slay vertcalblank oel evenel hsync blank el tntsc slay vertcalblank oel evenel hsync blank el slay slay vertcalblank oel evenel hsync blank el slay tal
adv7190/adv7191 ?24? rev. b mode 1: master option hsync , blank , l reste r ts e te avav eete ht sync oe l ss a tst te l t e hsync ,,vrt blank blank avavccr ntsc al hsync , blank el el el ata al clock ntsc clock c y c y hsync blank al clock ntsc clock toets so hsync , vsync, blank reste r ts e te avav ets ht vet sync ss a et tst t hsync vs ync oa vsync hsync et blank b lank ,avav ccrntscal slay slay vertcalblank oel evenel hsync blank vsync oel evenel slay slay vertcalblank hsync blank vsync tntsc
adv7190/adv7191 ?25? rev. b 622 623 624 625 1234 5 67 21 22 23 display vertical blank odd field even field hsync blank vsync slay slay vertcalblank oel evenel hsync blank slay vsync tal o hsync , vsync , blank reste r ts e te avav eete ht vet sync ss a et tst t hsync vsync oa vsync hsync et blank blank avav ccr ntscal hsync , blank vsync hsync , blank vsync al clock ntsc clock hsync vsync blank el ata al clock ntsc clock c y c y teots al clock ntsc clock al clock ntsc clock hsync vsync blank el ata al clock ntsc clock c y c y c toets
adv7190/adv7191 ?26? rev. b mode 3: master/slave option hsync , blank , l reste r ts e te avav ets eetes ht sync oe l ss a tst te l t e hsync ,,vrt blank blank avavccr ntsc al oel evenel slay slay vertcalblank hsync blank el slay slay vertcalblank oel evenel hsync blank el tntsc slay vertcalblank oel evenel hsync blank el slay slay vertcalblank oel evenel hsync blank el slay tal
rev. b adv7190/adv7191 C27C mpu port description the adv7190/adv7191 supports a two-wire serial (i 2 c- compatible) microprocessor bus driving multiple peripherals. two i nputs, serial data (sda) and serial clock (scl), carry infor mation between any device connected to the bus. each slave device is re cognized by a unique addre ss. the adv7190/ adv7191 has four possible slave addresses for both read and write operations. these are unique addresses for each device and are illustrated in fi gure 46 and figure 47. the lsb sets either a read or write operation. l ogic level 1 corresponds to a read operation while logic level 0 corresponds to a write op era- t ion. a1 is set by setting the alsb pin of the adv7190/adv7191 to logic level 0 or logic level 1. 1 x 10101a1 address control setup by alsb read/write control 0 write 1 read figure 46a. slave address for adv7190 0 x 10101a1 address control setup by alsb read/write control 0 write 1 read figure 46b. slave address for adv7191 to control the various devices on the bus the following protocol m ust be followed. first, the master initiates a data transfer by establishing a start condition, de?ed by a high-to-low transition on sda while scl remains high. this indicates that an address/ data stream will follow. all peripherals respond to the start cond ition and shift the next eight bits (7-bit address + r/ w bit). the bits are transferred from msb down to lsb. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an acknowledge b it. all other devices withdraw from the bus at this point and maintain an idle condition. the idle condition is where the device monitors the sda and scl lines waiting for the start condi tion and the correct transmitted address. the r/ w bit determines the direction of the data. a logic 0 on the lsb of the ?st byte means that the master will write information to the peripheral. a logic 1 on the lsb of the ?st byte means that the master will read information from the peripheral. the adv7190/adv7191 acts as a standard slave device on the bus. the data on the sda pin is eight bits long supporting the 7-bit addresses p lus the r/ w bit. it interprets the ?st byte as the device ad dress and the second byte as the starting subaddress. the subaddresses autoincrement allowing data to be written to or read from the starting subaddress. a data transfer is always terminated by a stop condition. the user can also access any unique subad dress register on a one-by-one basis without having to update all the registers. there is one exception. the subcarrier frequency registers should be updated in sequence, starting with subcarrier frequency register 0. the autoincrement function should be then used to increment and access subcarrier fre quency registers 1, 2, and 3. the subcarrier frequency registers should not be accessed independently. stop and start conditions can be detected at any stage du ring the data transfer. if these conditions are asserted out of se quence with normal read and write operations, they cause an immediate jump to the idle condition. during a given scl high period the user should issue only one start condition, one stop c ondition, or a single stop condition followed by a single start condition. if, an invalid subaddress is issued by the user, the adv7190/ adv7191 will not issue an acknowledge and will return to the idle condition. if in autoincrement mode, the user exceeds the highest subaddress, the following action will be taken: 1. in read mode, the highest subaddress register contents will continue to be ou tput until the master dev ice issues a no- acknowledge. this indicates the end of a read. a no- acknowledge condition is where the sda line is not pulled low on the ninth pulse. 2. in write mode, the data for the invalid byte will be not be loaded into any subaddress register, a no-acknowledge will be issued by the adv7190/adv7191 and the part will re turn to the idle condition. 89 89 89 p s start addr r/ w ack subaddress ack data ack stop sdata sclock 1?7 1?7 1?7 figure 47. bus data transfer fig ure 47 illustrates an example of data transfer for a read s equence and the start and stop conditions. figure 48 shows bus write and read sequences. data a(s) s slave addr a(s) sub addr a(s) lsb = 0 lsb = 1 data a (s) p s slave addr a(s) sub addr a(s) s slave addr a(s) data a(m) a (m ) data p write sequence read sequence a (s) = no acknowledge by slave a (m) = no acknowledge by master a(s) = acknowledge by slave a(m) = acknowledge by master s = start bit p = stop bit figure 48. write and read sequences
rev. b adv7190/adv7191 C28C register accesses the mpu can write to or read from all of the registers of the adv7 190/adv7191 with the exception of the subaddress regis- te rs, which are write-only registers. the subaddress r egister determines which register the next read or write operation ac cesses. all communications with the part through the bus start with an access to the subaddress register. then a read/write operation is performed from/to the target address which then increments to the next address until a stop command on the bus is performed. register programming the following section describes each register. all registers can be read from as well as written to. subaddress register (sr7?r0) the communications register is an eight bit write-only register. after the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. the subaddress r egister determines to/from which register the operation takes place. figure 49 shows the various operations under the control of the subaddress register 0 should always be written to sr7. register select (sr6?r0) these bits are set up to point to the required starting address. address sr6 sr5 sr4 sr3 sr2 sr1 sr0 00h 0 0 0 0 0 0 0 mode register 0 01h 0 0 0 0 0 0 1 mode register 1 02h 0 0 0 0 0 1 0 mode register 2 03h 0 0 0 0 0 1 1 mode register 3 04h 0 0 0 0 1 0 0 mode register 4 05h 0 0 0 0 1 0 1 mode register 5 06h 0 0 0 0 1 1 0 mode register 6 07h 0 0 0 0 1 1 1 mode register 7 08h 0 0 0 1 0 0 0 mode register 8 09h 0 0 0 1 0 0 1 mode register 9 0ah 0 0 0 1 0 1 0 timing register 0 0bh 0 0 0 1 0 1 1 timing register 1 0ch 0 0 0 1 1 0 0 subcarrier frequency register 0 0dh 0 0 0 1 1 0 1 subcarrier frequency register 1 0eh 0 0 0 1 1 1 0 subcarrier frequency register 2 0fh 0 0 0 1 1 1 1 subcarrier frequency register 3 10h 0 0 1 0 0 0 0 subcarrier phase register 11h 0 0 1 0 0 0 1 closed captioning extended data byte 0 12h 0 0 1 0 0 1 0 closed captioning extended data byte 1 13h 0 0 1 0 0 1 1 closed captioning data byte 0 14h 0 0 1 0 1 0 0 closed captioning data byte 1 15h 0 0 1 0 1 0 1 ntsc pedestal/teletext control register 0 16h 0 0 1 0 1 1 0 ntsc pedestal/teletext control register 1 17h 0 0 1 0 1 1 1 ntsc pedestal/teletext control register 2 18h 0 0 1 1 0 0 0 ntsc pedestal/teletext control register 3 19h 0 0 1 1 0 0 1 cgms/wss 0 1ah 0 0 1 1 0 1 0 cgms/wss 1 1bh 0 0 1 1 0 1 1 cgms/wss 2 1ch 0 0 1 1 1 0 0 teletext request control register 1dh 0 0 1 1 1 0 1 contrast control register 1eh 0 0 1 1 1 1 0 u scale 1fh 0 0 1 1 1 1 1 v scale 20h 0 1 0 0 0 0 0 hue adjust control register 21h 0 1 0 0 0 0 1 brightness control register 22h 0 1 0 0 0 1 0 sharpness control register 23h 0 1 0 0 0 1 1 dnr 0 24h 0 1 0 0 1 0 0 dnr 1 25h 0 1 0 0 1 0 1 dnr 2 26h 0 1 0 0 1 1 0 gamma correction register 0 27h 0 1 0 0 1 1 1 gamma correction register 1 28h 0 1 0 1 0 0 0 gamma correction register 2 29h 0 1 0 1 0 0 1 gamma correction register 3 2ah 0 1 0 1 0 1 0 gamma correction register 4 2bh 0 1 0 1 0 1 1 gamma correction register 5 2ch 0 1 0 1 1 0 0 gamma correction register 6 2dh 0 1 0 1 1 0 1 gamma correction register 7 2eh 0 1 0 1 1 1 0 gamma correction register 8 2fh 0 1 0 1 1 1 1 gamma correction register 9 30h 0 1 1 0 0 0 0 gamma correction register 10 31h 0 1 1 0 0 0 1 gamma correction register 11 32h 0 1 1 0 0 1 0 gamma correction register 12 33h 0 1 1 0 0 1 1 gamma correction register 13 34h 0 1 1 0 1 0 0 brightness detect register 35h 0 1 1 0 1 0 1 output clock register 36h 0 1 1 0 1 1 0 reserved 37h 0 1 1 0 1 1 1 reserved 38h 0 1 1 1 0 0 0 reserved 39h 0 1 1 1 0 0 1 reserved 3ah 0 1 1 1 0 1 0 macrovision register (adv7190 only) 3bh 0 1 1 1 0 1 1 macrovision register (adv7190 only) 3ch 0 1 1 1 1 0 0 macrovision register (adv7190 only) 3dh 0 1 1 1 1 0 1 macrovision register (adv7190 only) 3eh 0 1 1 1 1 1 0 macrovision register (adv7190 only) 3fh 1 1 1 1 1 1 1 macrovision register (adv7190 only) 40h 1 0 0 0 0 0 0 macrovision register (adv7190 only) 41h 1 0 0 0 0 0 1 macrovision register (adv7190 only) 42h 1 0 0 0 0 1 0 macrovision register (adv7190 only) 43h 1 0 0 0 0 1 1 macrovision register (adv7190 only) 44h 1 0 0 0 1 0 0 macrovision register (adv7190 only) 45h 1 0 0 0 1 0 1 macrovision register (adv7190 only) 46h 1 0 0 0 1 1 0 macrovision register (adv7190 only) 47h 1 0 0 1 1 1 1 macrovision register (adv7190 only) 48h 1 0 0 1 0 1 0 macrovision register (adv7190 only) 49h 1 0 0 1 0 0 1 macrovision register (adv7190 only) 4ah 1 0 0 1 0 0 0 macrovision register (adv7190 only) 4bh 1 0 0 1 0 1 1 macrovision register (adv7190 only) adv7190/adv7191 subaddress register sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 sr7 zero should be written here figure 49. subaddress register
rev. b C29C adv7190/adv7191 mode register 0 mr0 (mr07?r00) ( address (sr4?r0) = 00h) fi gure 50 shows the various operations under the control of mode register 0. mr0 bit description output video standard selection (mr00?r01) these bits are used to set up the encoder mode. the adv7190/ adv7191 can be set up to output ntsc, pal (b, d, g, h, i), pal m or pal n standard video. luminance filter select (mr02?r04) these bits specify which luma ?ter is to be selected. the ?ter s election is made independent of whether pal or ntsc is selected. chrominance filter select (mr05?r07) these bits select the chrominance ?ter. a low-pass ?ter can be selected with a choice of cut-off frequencies (0.65 mhz, 1.0 mhz, 1.3 mhz, 2 mhz, or 3 mhz) along with a choice of cif or qcif ?ters. mode register 1 mr1 (mr17?r10) (address (sr4?r0) = 01h) fi gure 51 shows the various operations under the control of mode register 1. mr1 bit description dac control (mr10?r15) bits mr15?r10 can be used to power down the dacs. this is used to reduce the power consumption of the adv7190/adv7191 or if any of the dacs are not required in the application. 4 oversampling control (mr16) to enable 4 oversampling this bit has to be set to 1. when en abled, the data is output at a frequency of 54 mhz. note that pll enable control has to be enabled (mr61 = 0) in 4 oversampling mode. reserved (mr17) a logical 0 must be written to this bit. mr07 mr06 mr05 mr04 mr03 mr02 mr01 mr00 chroma filter select 0 0 0 1.3 mhz low-pass filter 0 0 1 0.65 mhz low-pass filter 0 1 0 1.0 mhz low-pass filter 0 1 1 2.0 mhz low-pass filter 1 0 0 reserved 1 0 1 cif 1 1 0 qcif 1 1 1 3.0 mhz low-pass filter mr07 mr06 mr05 mr04 mr03 mr02 luma filter select 0 0 0 low-pass filter (ntsc) 0 0 1 low-pass filter (pal) 0 1 0 notch filter (ntsc) 0 1 1 notch filter (pal) 1 0 0 extended mode 1 0 1 cif 1 1 0 qcif 1 1 1 reserved mr01 mr00 0 0 ntsc 0 1 pal (b, d, g, h, i) 1 0 pal (m) (adv7190 only) 1 1 pal (n) output video standard selection figure 50. mode register 0 (mr0) mr17 mr16 mr15 mr14 mr13 mr12 mr11 mr10 dac a dac control 0 power-down 1 normal mr15 dac c dac control 0 power-down 1 normal mr13 dac e dac control 0 power-down 1 normal mr11 4 oversampling control 02 oversampling 14 oversampling mr16 dac b dac control 0 power-down 1 normal mr14 dac d dac control 0 power-down 1 normal mr12 dac f dac control 0 power-down 1 normal mr10 mr17 zero must be written to this bit figure 51. mode register 1 (mr1)
rev. b adv7190/adv7191 C30C mode register 2 mr2 (mr27?r20) (address (sr4?r0) = 02h) mode register 2 is an 8-bit-wide register. figure 52 shows the various operations under the control of mode register. mr2 bit description rgb/yuv control (mr20) this bit enables the output from the small or large dacs to be set to yuv or rgb output video standard. dac output control (mr21) this bit controls the output from dacs a, b, and c. when this bit is set to 1, composite, luma, and chroma signals are out- put from dacs a, b, and c (respectively). when this bit is set to 0, rgb or yuv may be output from these dacs. scart enable control (mr22) this bit is used to switch the dac outputs from scart to a euroscart con?uration. a complete table of all dac output con?urations is shown in table iii. pedestal control (mr23) t his bit speci?s whether a pedestal is to be generated on the ntsc composite video signal. this bit is invalid when the de vice is con?ured in pal mode. square pixel control (mr24) this bit is used to set up square pixel mode. this is available in slave mode only. for ntsc, a 24.5454 mhz clock must be supplied. for pal, a 29.5 mhz clock must be supplied. square pixel operation is not available in 4 oversampling mode. standard i 2 c control (mr25) t his bit controls the video standard used by the adv7190/ adv7191. when this bit is set to 1 the video standard as programmed in output video standard selection (mr00, mr01). w hen mr25 is set to 0, the adv7190/adv7191 is forced into the standard selected by the ntsc_pal pin. when ntsc_pal is low the standard is ntsc, when the ntsc_pal pin is high, the standard is pal. pixel data valid control (mr26) after resetting the device, this bit has the value 0 and the pixel data input to the encoder is blanked such that a black screen is output from the dacs. the adv7190/adv7191 will be set to master mode timing. when this bit is set to 1 by the user ( via the i 2 c), pixel data passes to the pins and the encoder re verts to the timing mode de?ed by timing register 0. sleep mode control (mr27) when this bit is set (1), sleep mode is enabled. with this mode e nabled, the adv7190/adv7191 current consumption is reduced to less than 1 ma. the i 2 c registers can be written to and read from when the adv7190/adv7191 is in sleep mode. when the device is in sleep mode and 0 is written to mr27, the adv7190/adv7191 will come out of sleep mode and resume normal operation. also, if a reset is applied during sleep mode, the a dv7190/adv7191 will come out of sleep mode and resume normal operation. for this to operate, power up in sleep mode control has to be enabled (mr60 = 0), otherwise sleep mode is con trolled by the pal_ntsc and screset/rtc/tr pins. table iii. dac output con?uration matrix scart dac o/p rgb/yuv mr22 mr21 mr20 dac a dac b dac c dac d dac e dac f 0 00g br cvbs luma chroma 0 01y uv cvbs luma chroma 0 10 cvbs luma chroma g b r 0 11 cvbs luma chroma y u v 1 00 cvbs b r g luma chroma 1 01 cvbs u v y luma chroma 1 10 cvbs luma chroma g b r 1 11 cvbs luma chroma y u v mr27 mr26 mr25 mr24 mr23 mr22 mr21 mr20 rgb/yuv control 0 rgb output 1 yuv output mr20 scart enable control 0 disable 1 enable mr22 square pixel control 0 disable 1 enable mr24 pixel data valid control 0 disable 1 enable mr26 dac output control 0 rgb/yuv/comp 1 comp/luma/chroma mr21 pedestal control 0 pedestal off 1 pedestal on mr23 standard i 2 c control 0 disable 1 enable mr25 sleep mode control 0 disable 1 enable mr27 figure 52. mode register 2 (mr2)
rev. b adv7190/adv7191 C31C mode register 3 mr3 (mr37?r30) ( address (sr4?r0) = 03h) mode register 3 is an 8-bit-wide register. figure 53 shows the various operations under the control of mode register 3. mr3 bit description revision code (mr30?r31) this bit is read only and indicates the revision of the device. vbi_open (mr32) this bit determines whether or not data in the vertical blanking interval (vbi) is output to the analog outputs or blanked. note t hat this condition is also valid in timing slave mode 0. for further information see vertical blanking data insertion and blank input section. teletext enable (mr33) t his bit must be set to 1 to enable teletext data insertion on th e ttx pin. teletext bit request mode control (mr34) this bit enables switching of the teletext request signal from a continuous high signal (mr34 = 0) to a bitwise request signal (mr34 = 1). c losed captioning field control (mr35?r36) these bits control the ?lds that closed captioning data is dis- played on, closed captioning information can be displayed on an od d ?ld, even ?ld or both ?lds. reserved (mr37) a logic 0 must be written to this bit. mode register 4 mr4 (mr47?r40) ( address (sr4?r0) = 04h) mode register 4 is an 8-bit-wide register. figure 54 shows the various operations under the control of mode register 4. mr4 bit description vsync_3h control (mr40) when this bit is enabled (1) in slave mode, it is possible to drive the vsync input low for 2.5 lines in pal mode and t hree lines in ntsc mode. when this bit is enabled in master mode the adv7190/adv7191 outputs an active low vs ync s ignal for three lines in ntsc mode and 2.5 lines in pal mode. genlock control (mr41?r42) th ese bits control the genlock feature and timing reset of the adv7190/adv7191. setting mr41 and mr42 to logic 0 disables the screset/rtc/tr pin and allows the adv7190/ adv7191 to operate in normal mode. 1. by setting mr41 to zero and mr42 to one a timing reset is applied, resetting the horizontal and vertical counters. this has the effect of resetting the field count to field 0. if the screset/rtc/tr pin is held high, the counters will remain reset. once the pin is released the counters will commence counting again. for correct counter reset, the screset/rtc/tr pin has to remain high for at least 37 ns (one clock cycle at 27 mhz). 2. if mr41 is set to one and mr42 is set to zero, the sc reset/ rtc/tr pin is con?ured as a subcarrier reset input and the subcarrier phase will reset to field 0 whenever a low-to- high transition is detected on the screset/rtc/tr pin (sch phase resets at the start of the next ?ld). 3. if mr41 is set to one and mr42 is set to one, the screset/ rtc/tr pin is con?ured as a real-time control input and t he adv7190/adv7191 can be used to lock to an external v ideo source working in rtc mode. for more inf ormation see real- time control, subcarrier reset and timing reset section. active video line duration (mr43) t his bit switches between two active video line durations. a zero sele cts ccir rec. 601 (720 pixels pal/ntsc) and a one s elects itu-r bt. 470 standard for active video duration (710 pixels ntsc, 702 pixels pal). chrominance control (mr44) this bit enables the color information to be switched on and off the chroma composite, color component outputs. burst control (mr45) this bit enables the color burst to be switched on and off the chroma and composite outputs. color bar control (mr46) t his bit can be used to generate and output an internal color bar test pattern. the color bar con?uration is 100/7.5/75/7.5 for ntsc and 100/0/75/0 for pal. it is important to note that when color bars are enabled the adv7190/adv7191 is con- ?ured in a master timing mode. mr37 zero must be written to this bit mr37 mr36 mr35 mr34 mr33 mr32 mr31 mr30 mr31 mr30 reserved for revision code vbi open 0 disable 1 enable mr32 ttx bit request mode control 0 disable 1 enable mr34 teletext enable 0 disable 1 enable mr33 closed captioning field control mr36 mr35 0 0 no data out 01 odd field only 10 even field only 11 data out (both fields) figure 53. mode register 3 (mr3)
rev. b adv7190/adv7191 C32C interlaced mode control (mr47) this bit is used to setup the output to interlaced or noninter- laced mode. mode register 5 mr5 (mr57?r50) (address (sr4?r0) = 05h) mode register 5 is an 8-bit-wide register. figure 55 shows the various operations under the control of mode register 5. mr5 bit description y-level control (mr50) t his bit controls the component y output level on the adv7 190/ adv7191. if this bit is set (0), the encoder outputs betacam levels when con?ured in pal or ntsc mode. if this bit is set (1), the encoder outputs smpte levels when con?ured in pal or ntsc mode. uv-levels control (mr51?r52) these bits control the component u and v output levels on the adv7190/adv7191. it is possible to have uv levels with a peak-to-peak amplitude of either 700 mv (mr52 + mr51 = 01 ) or 1000 mv (mr52 + mr51 = 10) in ntsc and pal. it is also possible to have default values of 934 mv for ntsc and 700 mv for pal (mr52 + mr51 = 00). rgb sync (mr53) this bit is used to set up the rgb outputs with the sync infor- mation encoded on all rgb outputs. clamp delay value (mr54?r55) these bits control the delay or advance of the clamp signal in the front or back porch of the adv7190/adv7191. it is possible to delay or advance the pulse by zero, one, two, or three clock cycles. note: pin 51 is a multifunctional pin ( vso /clamp). clamp/ vso select control (mr77) has to be set accordingly. clamp delay direction (mr56) this bit controls a positive or negative delay in the clamp signal. if this bit is set (1), the delay is negative. if it is set (0), the delay is positive. clamp position (mr57) this bit controls the position of the clamp signal. if this bit is set (1), the clamp signal is located in the back porch position. if this bit is set (0), the clamp signal is located in the front porch position. mr47 mr46 mr45 mr44 mr43 mr42 mr41 mr40 0 disable 1 enable mr46 color bar control chrominance control 0 enable color 1 disable color mr44 genlock control mr42 mr41 0 0 disable genlock 01 enable subcarrier reset pin 10 timing reset 11 enable rtc pin 0 disable 1 enable mr40 vsync 3h control burst control 0 enable burst 1 disable burst mr45 active video line duration 0 720 pixels 1 710 pixels/702 pixels mr43 interlaced mode control 0 interlaced 1 noninterlaced mr47 figure 54. mode register 4 (mr4) mr57 mr56 mr55 mr54 mr53 mr52 mr51 mr50 0 positive 1 negative mr56 clamp delay direction uv level control mr52 mr51 0 0 default levels 01 700mv 10 1000mv 11 reserved 0 disable 1 enable mr53 rgb sync clamp position 0 front porch 1 back porch mr57 0 disable 1 enable mr50 y level control clamp delay mr55 mr54 0 0 no delay 011 pclk 102 pclk 113 pclk figure 55. mode register 5 (mr5)
rev. b adv7190/adv7191 C33C mode register 6 mr6 (mr67?r60) (address (sr4?r0) = 06h) mode register 6 is an 8-bit-wide register. figure 56 shows the various operations under the control of mode register 6. mr6 bit description power-up sleep mode control (mr60) after reset is applied this control is enabled (mr60 = 0) if both screset/rtc/tr and ntsc_pal pins are tied high. the adv7190/adv7191 will then power up in sleep mode to facilitate low power consumption while the i 2 c is initialized. w hen this control is disabled (mr60 = 1, via the i 2 c) sleep mode c ontrol passes to sleep mode control, mr27. ppl enable control (mr61) the pll control should be enabled (mr61 = 0 ) when 4 oversampling is enabled (mr16 = 1). it is also used to reset the pll when this bit is toggled. reserved (mr62, mr63, mr64) a logic 0 must be written to these bits. field counter (mr65, mr66, mr67) these three bits are read-only bits. the ?ld count can be read back over the i 2 c interface. in ntsc mode the ?ld count goes from 0?, in pal mode from 0?. mode register 7 mr7 (mr77?r70) (address (sr4?r0) = 07h) mode register 7 is an 8-bit-wide register. figure 57 shows the various operations under the control of mode register 7. mr7 bit description color control enable (mr70) this bit is used to enable control of contrast and saturation of color. if this bit is set (1), color controls are enabled (contrast control register, u-scale register, v-scale register). if this bit is set (0), the color control features are disabled. luma saturation control (mr71) when this bit is set (1), the luma signal will be clipped if it reaches a limit that corresponds to an input luma value of 255 (after scaling by the contrast control register). this prevents the chrominance component of the composite video signal being clipped if the amplitude of the luma is too high. when this bit is set (0), this control is disabled. hue adjust control (mr72) this bit is used to enable hue adjustment on the composite and chroma output signals of the adv7190/adv7191. when this bit is set (1), the hue of the color is adjusted by the phase offset described in the hue adjust control register. when this bit is set (0), hue adjustment is disabled. brightness enable control (mr73) this bit is used to enable the brightness control of the adv7190/ adv7191. the actual brightness level is programmed in the brightness control register. this value or ?etup?level is added to the scaled y data. when this bit is set (1), brightness control is enabled. when this bit is set (0), brightness control is disabled. sharpness filter enable (mr74) this bit is used to enable the sharpness control of the luminance s ignal on the adv7190/adv7191 (luma filter select has to be set to extended, i.e., mr04?r02 = 100). the various re sponses of the ?ter are determined by the sharpness con- trol register. when this bit is set (1), the luma response is altered by the amount described in the sharpness control register. when this bit is set (0), the sharpness control is disabled. see internal filter response section for luma signal responses. cso_hso output control (mr75) this bit is used to determine whether hso or cso ttl output signal is output at the cso_hso pin. if this bit is set (1), the cso ttl signal is output. if this bit is set 0, the hso ttl signal is output. mr67 mr66 mr65 mr64 mr63 mr62 mr61 mr60 0 enabled 1 disabled mr60 power-up sleep mode control 0 enabled 1 disabled mr61 pll enable control zero must be written to these bits mr64 mr63 mr62 field counter mr67 mr66 mr65 figure 56. mode register 6 (mr6) zero must be written to this bit mr76 mr77 mr76 mr75 mr74 mr73 mr72 mr71 mr70 0 disable 1 enable mr74 sharpness filter enable 0 vso output 1 clamp output mr77 clamp/ vso select 0 disable 1 enable mr70 color control enable cso_hso output control 0 hso out 1 cso out mr75 0 disable 1 enable mr72 hue adjust control 0 disable 1 enable mr73 brightness enable control 0 disable 1 enable mr71 luma saturation control figure 57. mode register 7 (mr7)
rev. b adv7190/adv7191 C34C reserved (mr76) a logic 0 must be written to this bit. clamp/ vso select (mr77) this bit is used to select the functionality of pin 51. a 1 selects clamp as the output signal. a 0 selects vso output. mode register 8 mr8 (mr87?r80) ( address (sr4?r0) = 08h) mode register 8 is an 8-bit-wide register. figure 58 shows the various operations under the control of mode register 8. mr8 bit description reserved (mr80, mr81) a logic 0 must be written to these bits. double buffer control (mr82) d ouble buffering can be enabled or disabled on the contrast control register, u scale register, v scale register, hue a djust control register, closed captioning register, brightness con- trol register, gamma curve select bit and the macrovision registers (adv7190 only). double buffering is not available in master timing mode. 16-bit pixel port (mr83) this bit controls if the adv7190/adv7191 accepts 8-bit or 16-bit input data. in 8-bit mode the data will be input on pins p 0? 7. unused pixel inputs should be grounded. reserved (mr84) a logic 0 must be written to this bit. dnr enable control (mr85) to enable the dnr process this bit has to be set to 1. if this bit is set to 0, the dnr processing is bypassed. for further infor- ma tion on dnr controls see dnr registers 2?, dnr1 bit description, and dnr2 bit description sections. gamma enable control (mr86) to enable the programmable gamma correction this bit has to be set to enabled (mr86 is set to 1). for further information on gamma correction controls see gamma correction registers 0?3 (gamma 0?3) (address (sr5?r0) = 26h?2h) section. gamma curve select control (mr87) this bit selects which of the two programmable gamma curves is used. when setting mr87 to 0, the gamma correction c urve to be processed is curve a. otherwise, curve b is selected. for fur- t her information on gamma correction controls see gamma correction registers 0 ?3 (gamma 0?3) (address (sr5?r0) = 26h?2h) section. mode register 9 mr9 (mr97?r90) (address (sr4?r0) = 09h) mode register 9 is an 8-bit-wide register. figure 59 shows the various operations under the control of mode register 9. mr9 bit description undershoot limiter (mr90?r91) this control ensures that no luma video data will go below a programmable level. this prevents any synchronization problems due to luma signals going below the blanking level. available limit levels are ?.5 ire, ? ire, ?1 ire. note that this facility is only available in 4 oversampling mode (mr16 = 1). when the device is operated in 2 oversampling mode (mr16 = 0) or rgb outputs without rgb sync are selected, the minimum luma level is set in timing r egister 0, tr06 (min luma control). reserved (mr92?r93) a logic 0 must be written to these bits. chroma delay control (mr94?r95) the chroma signal can be delayed by up to 296 ns (eight clock cycles at 27 mhz) using mr94?r95. for further informa- tion see also chroma/luma delay section. reserved (mr96?r97) a logic 0 must be written to these bits. zero must be written to this bit mr84 mr87 mr86 mr85 mr84 mr83 mr82 mr81 mr80 0 8-bit pixel port 1 16-bit pixel port mr83 16-pixel port dnr enable control mr85 0 disable 1 enable 0 disable 1 enable mr82 double buffer control zero must be written to these bits mr81 mr80 0 disable 1 enable mr86 gamma enable control 0 curve a 1 curve b mr87 gamma curve select control figure 58. mode register 8 (mr8) mr97 mr96 mr95 mr94 mr93 mr92 mr91 mr90 zero must be written to these bits mr93 mr92 zero must be written to these bits mr97 mr96 chroma delay control mr95 mr94 0 0 0ns delay 01 148ns delay 10 296ns delay 11 reserved undershoot limiter mr91 mr90 0 0 disabled 01 ?11 ire 10 ?6 ire 11 ?1.5 ire figure 59. mode register 9 (mr9)
rev. b adv7190/adv7191 C35C timing register 0 (tr07?r00) (address (sr4?r0) = 0ah) figure 60 shows the various operations under the control of t iming register 0. this register can be read from as well as written to. tr0 bit description master/slave control (tr00) this bit controls whether the adv7190/adv7191 is in master or slave mode. timing mode selection (tr01?r02) these bits control the timing mode of the adv7190/adv7191. these modes are described in more detail in the video tim- in g description and reset sequence sections of the data sheet. blank input control (tr03) this bit controls whether the blank input is used to accept blank signals or whether blank signals are internally generated. note: when this input pin is tied high (to 5 v), the input is disabled regardless of the register setting. it, therefore, should be tied low (to ground) to allow control over the i 2 c register. luma delay (tr04?r05) t he luma signal can be delayed by up to 222 ns (or six clock cy cles at 27 mhz) using tr04?r05. for further information see chroma/luma delay section. min luminance value (tr06) t his bit is used to control the minimum luma output value by the adv7190/adv7191 in 2 oversampling mode (mr 16 = 0). when this bit is set to a logic 1, the luma is limited to 7.5ire below the blank level. when this bit is set to (0), the luma value can be as low as the sync bottom level (40ire below blanking). timing register reset (tr07) toggling tr07 from low to high and low again resets the inter- nal timing counters. this bit should be toggled after power-up, reset, or changing to a new timing mode. timing register 1 ( tr17?r10) ( address (sr4?r0) = 0bh) timing register 1 is an 8-bit-wide register. figure 61 shows the various operations under the control of timing register 1. this register can be read from as well written to. this register can be used to adjust the width and position of the master mode timing signals. tr1 bit description hsync width (tr10?r11) t hese bits adjust the hsync pulsewidth. t pclk = one clock cycle at 27 mhz. hsync to vsync delay control (tr12?r13) these bits adjust the position of the hsync output relative to the vsync output. t pclk = one clock cycle at 27 mhz. hsync to vsync rising edge control (tr14?r15) when the adv7190/adv7191 is in timing mode 1, these bits adjust the position of the hsync output relative to the vsync output rising edge. t pclk = one clock cycle at 27 mhz. vsync width (tr14?r15) when the adv7190/adv7191 is con?ured in timing mode 2, these bits adjust the vsync pulsewidth. t pclk = one clock cycle at 27 mhz. hsync to pixel data adjust (tr16?r17) this enables the hsync to be adjusted with respect to the pixel data. this allows the cr and cb components to be swapped. this adjustment is available in both master and slave timing modes. t pclk = one clock cycle at 27 mhz. tr07 tr06 tr05 tr04 tr03 tr02 tr01 tr00 0 luma min = sync bottom 1 luma min = blank ?7.5 ire tr06 min luminance value 0 enable 1 disable tr03 blank input control timing register reset tr07 0 slave timing 1 master timing tr00 master / slave control luma delay tr05 tr04 0 0 0ns delay 01 74ns delay 10 148ns delay 11 222ns delay tr02 tr01 0 0 mode 0 01 mode 1 10 mode 2 11 mode 3 timing mode control figure 60. timing register 0
rev. b adv7190/adv7191 C36C subcarrier frequency registers 3? (fsc31?sc0) (address (sr4?r0) = 0ch?fh) these 8-bit-wide registers are used to set up the subcarrier frequency. the value of these registers are calculated by using the following equation: subcarrier frequency f f scf clk register = () 21 32 example : ntsc mode, f clk = 27 mhz , f scf = 3.5795454 mhz subcarrier frequency alue v = () 21 3 5795454 10 27 10 32 6 6 ? subcarrier register value = 21f07c16 hex fi g ure 62 shows how the frequency is set up by the four registers. fsc31 fsc30 fsc29 fsc28 fsc27 fsc26 fsc25 fsc24 subcarrier frequency reg 3 fsc23 fsc22 fsc21 fsc20 fsc19 fsc18 fsc17 fsc16 subcarrier frequency reg 2 subcarrier frequency reg 1 fsc7 fsc6 fsc5 fsc4 fsc3 fsc2 fsc1 fsc0 subcarrier frequency reg 0 fsc15 fsc14 fsc13 fsc12 fsc11 fsc10 fsc9 fsc8 figure 62. subcarrier frequency registers subcarrier phase register (fph7?ph0) (address (sr4?r0) = 10h) this 8-bit-wide register is used to set up the subcarrier phase. each bit represents 1.41 . for normal operation this register is set to 00hex. fph7 fph6 fph5 fph4 fph3 fph2 fph1 fph0 subcarrier phase register figure 63. subcarrier phase register closed captioning even field data register 1? (ccd15?cd0) (address (sr4?r0) = 11?2h) t hese 8-bit-wide registers are used to set up the closed captio ning extended data bytes on even fields. figure 64 shows how the high and low bytes are set up in the registers. ccd15 ccd14 ccd13 ccd12 ccd11 ccd10 ccd9 ccd8 byte 1 ccd7 ccd6 ccd5 ccd4 ccd3 ccd2 ccd1 ccd0 byte 0 figure 64. closed captioning extended data register closed captioning odd field data register 1? (ced15?ed0) (subaddress (sr4?r0) = 13?4h) these 8-bit-wide registers are used to set up the closed captioning d ata bytes on odd fields. figure 65 shows how the high and low bytes are set up in the registers. ced15 ced14 ced13 ced12 ced11 ced10 ced9 ced8 byte 1 ced7 ced6 ced5 ced4 ced3 ced2 ced1 ced0 byte 0 figure 65. closed captioning data register tr17 tr16 tr15 tr14 tr13 tr12 tr11 tr10 tr17 tr16 0 0 0 t pclk 011 t pclk 102 t pclk 113 t pclk hsync to pixel data adjust tr15 tr14 t c 0 t b 1t b + 32 s hsync to vsync rising edge delay (mode 1 only) tr13 tr12 t b 0 0 0 t pclk 014 t pclk 108 t pclk 11 18 t pclk hsync to vsync delay tr11 tr10 t a 0 0 1 t pclk 014 t pclk 10 16 t pclk 11 128 t pclk hsync width tr15 tr14 0 0 1 t pclk 014 t pclk 10 16 t pclk 11 128 t pclk vsync width (mode 2 only) line 313 line 314 line 1 t b t a t c vsync hsync timing mode 1 (master/pal) figure 61. timing register 1
rev. b adv7190/adv7191 C37C ntsc pedestal/pal teletext control registers 3? ( pce15?, pco15?)/(txe15?, txo15?) (subaddress (sr4?r0) = 15?8h) these 8-bit-wide registers are used to enable the ntsc pedestal/ p al teletext on a line-by-line basis in the vertical blanking interval for both odd and even ?lds. figures 66 and 67 show the four control registers. a logic 1 in any of the bits of these registers has the effect of turning the pedestal off on the equiva- l ent line when used in ntsc. a logic 1 in any of the bits of these registers has the effect of turning teletext on on the equivalent line when used in pal. pco7 pco6 pco5 pco4 pco3 pco2 pco1 pco0 field 1/3 pco15 pco14 pco13 pco12 pco11 pco10 pco9 pco8 field 1/3 pce15 pce14 pce13 pce12 pce11 pce10 pce9 pce8 pce7 pce6 pce5 pce4 pce3 pce2 pce1 pce0 line 17 line 16 line 15 line 14 line 13 line 12 line 11 line 10 line 25 line 24 line 23 line 22 line 21 line 20 line 19 line 18 line 17 line 16 line 15 line 14 line 13 line 12 line 11 line 10 line 25 line 24 line 23 line 22 line 21 line 20 line 19 line 18 field 2/4 field 2/4 figure 66. pedestal control registers txo7 txo6 txo5 txo4 txo3 txo2 txo1 txo0 field 1/3 txo15 txo14 txo13 txo12 txo11 txo10 txo9 txo8 field 1/3 txe15 txe14 txe13 txe12 txe11 txe10 txe9 txe8 txe7 txe6 txe5 txe4 txe3 txe2 txe1 txe0 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 line 22 line 21 line 20 line 19 line 18 line 17 line 16 line 15 field 2/4 field 2/4 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 line 22 line 21 line 20 line 19 line 18 line 17 line 16 line 15 figure 67. teletext control registers te letext request control register (tc07?c00) (address (sr4?r0) = 1ch) t eletext control register is an 8-bit-wide register. see figure 68. ttxreq falling edge control (tc00?c03) these bits control the position of the falling edge of ttxreq. it can be programmed from zero clock cycles to a maximum of 15 clock cycles. this controls the active window for teletext d ata. increasing this value reduces the amount of teletext bits below the default of 360. if bits tc00?c03 are 00hex when bits tc07?c04 are changed then the falling edge of ttreq will track that of the rising edge (i.e., the time between the fall- ing and rising edge remains constant). pclk = clock cycle at 27 mhz. ttxreq rising edge control (tc04?c07) these bits control the position of the rising edge of ttxreq. it can be programmed from zero clock cycles to a maximum of 15 clock cycles. pclk = clock cycle at 27 mhz. tc07 tc06 tc05 tc04 tc03 tc02 tc01 tc00 tc03 tc02 tc01 tc00 0 0 00 0 pclk 00 0 11 pclk '' '' '' '' '' pclk 11 1 01 4 pclk 11 1 11 5 pclk ttxreq falling edge control tc07 tc06 tc05 tc04 0 0 00 0 pclk 00 0 11 pclk '' '' '' '' '' pclk 11 1 0 14 pclk 11 1 1 15 pclk ttxreq rising edge control figure 68. teletext control register cgms_wss register 0 c/w0 (c/w07?/w00) (address (sr4?r0) = 19h) cgms_wss register 0 is an 8-bit-wide register. figure 69 shows the operations under control of this register. c/w0 bit description cgms data (c/w00?/w03) these four data bits are the ?al four bits of cgms data output stream. note it is cgms data only in these bit positions, i.e., wss data does not share this location. cgms crc check control (c/w04) when this bit is enabled (1), the last six bits of the cgms data, i .e., the crc check sequence, is internally calculated by the adv7190/adv7191. if this bit is disabled (0), the crc values in the register are output to the cgms data stream. cgms odd field control (c/w05) when this bit is set (1), cgms is enabled for odd ?lds. note this is only valid in ntsc mode. cgms even field control (c/w06) when this bit is set (1), cgms is enabled for even ?lds. note this is only valid in ntsc mode. wss control (c/w07) when this bit is set (1), wide screen signalling is enabled. note this is only valid in pal mode. c/w07 c/w06 c/w05 c/w04 c/w03 c/w02 c/w01 c/w00 0 disable 1 enable c/w07 wss control 0 disable 1 enable c/w05 cgms odd field control 0 disable 1 enable c/w06 cgms even field control 0 disable 1 enable c/w04 cgms crc check control c/w03 ? c/w00 cgms data figure 69. cgms_wss register 0
rev. b adv7190/adv7191 C38C cgms_wss register 1 c/w1 (c/w17?/w10) (address (sr4?r0) = 1ah) c gms_wss register 1 is an 8-bit-wide register. figure 70 shows the operations under control of this register. c/w1 bit description cgms/wss data (c/w10?/w15) these bit locations are shared by cgms data and wss data. in ntsc mode these bits are cgms data. in pal mode these bits are wss data. cgms data (c/w16?/w17) these bits are cgms data bits only. c/w17 c/w16 c/w15 c/w14 c/w13 c/w12 c/w11 c/w10 c/w15 ? c/w10 cgms/wss data c/w17 ? c/w16 cgms data figure 70. cgms_wss register 1 cgms_wss register 2 c/w1 (c/w27?/w20) ( address (sr4?r0) = 1bh) cgms_wss register 2 is an 8-bit-wide register. figure 71 shows the operations under control of this register. c/w2 bit description cgms/wss data (c/w20?/w27) these bit locations are shared by cgms data and wss data. in ntsc mode these bits are cgms data. in pal mode these bits are wss data. c/w27 ? c/w20 cgms/wss data c/w27 c/w26 c/w25 c/w24 c/w23 c/w22 c/w21 c/w20 figure 71. cgms_wss register 2 contrast control register (cc00?c07) (address (sr4?r0) = 1dh) the contrast control register is an 8-bit-wide register used to scale the y output levels. figure 72 shows the operation under control of this register. y scale value (cc00?c07) t hese eight bits represent the value required to scale the y pixel data from 0.0 to 1.5 of its initial level. the value of these eight bits is calculated using the following equation: y scale value = scale factor 128 example: scale factor = 1.18 y scale value = 1.18 128 = 151.04 y scale value = 151 (rounded to the nearest integer) y scale value = 10010111 b y scale value = 97 h cc07 ? cc00 y scale value cc07 cc06 cc05 cc04 cc03 cc02 cc01 cc00 figure 72. contrast control register color control registers 2? (cc2?c1) ( address (sr4?r0) = 1eh?fh) the color control registers are 8-bit-wide registers used to scale t he u and v output levels. figure 73 shows the operations under control of these registers. cc17 ? cc10 u scale value cc17 cc16 cc15 cc14 cc13 cc12 cc11 cc10 cc27 ? cc20 v scale value cc27 cc26 cc25 cc24 cc23 cc22 cc21 cc20 figure 73. color control registers cc1 bit description u scale value (cc10?c17) these eight bits represent the value required to scale the u level from 0.0 to 2.0 of its initial level. the value of these eight bits is calculated using the following equation: u scale value = scale factor 128 example: scale factor = 1.18 u scale value = 1.18 128 = 151.04 u scale value = 151 (rounded to the nearest integer) u scale value = 10010111 b u scale value = 97 h cc2 bit description v scale value (cc20?c27) these eight bits represent the value required to scale the v pixel data from 0.0 to 2.0 of its initial level. the value of these eight bits is calculated using the following equation: v scale value = scale factor 128 example: scale factor = 1.18 v scale value = 1.18 128 = 151.04 v scale value = 151 (rounded to the nearest integer) v scale value = 10010111 b v scale value = 97 h
rev. b adv7190/adv7191 C39C hue adjust control register (hcr) (address (sr5?r0) = 20h) t he hue control register is an 8-bit-wide register used to adjust the hue on the composite and chroma outputs. figure 74 shows the operation under control of this register. hcr7 ? hcr0 hue adjust value hcr7 hcr6 hcr5 hcr4 hcr3 hcr2 hcr1 hcr0 figure 74. hue adjust control register hcr bit description hue adjust value (hcr0?cr7) these eight bits represent the value required to vary the hue of t he video data, i.e., the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the colorburst. the adv7190/adv7191 provides a range of 22.5 increments of 0.17578125 . for normal operation (zero adjust- ment) this register is set to 80hex. ffhex and 00hex represent t he upper and lower limit (respectively) of adjustment attainable. h ue adjust [ ] = 0.17578125 (h cr d ?128); for positive hue adjust value example: to adjust the hue by 4 write 97 h to the hue adjust control register: (4/0.17578125) + 128 = 151 d * = 97 h to adjust the hue by (? ) write 69 h to the hue adjust control register: (?/0.17578125) + 128 = 10d d * = 69 h * rounded to the nearest integer. brightness control registers (bcr) ( address (sr5?r0) = 21h) the brightness register is an 8-bit-wide register which allows brightness control. figure 75 shows the operation under control of this register. bcr bit description brightness value (bcr0?cr6) s even bits of this 8-bit-wide register are used to control the brightness level. the brightness is controlled by adding a pro- grammable setup level onto the scaled y data. this brightness level can be a positive or negative value. the programmable brightness level in ntsc without pedestal an d pal are max 15 ire and min ?.5 ire, in ntsc with p edestal max 22.5 ire and min 0 ire. table iv. brightness control register value s etup setup brightness level in level in setup control ntsc with ntsc no level in register pedestal pedestal pal value 22.5 ire 15 ire 15 ire 1e h 15 ire 7.5 ire 7.5 ire 0f h 7.5 ire 0 ire 0 ire 00 h 0 ire ?.5 ire 7.5 ire 71 h note values in the range from 3f h to 44 h might result in an invalid output signal. example 1. standard: ntsc with pedestal. to add +20 ire brightness level, write 28 h into the brightness control register: [ brightness control register value ] h = [ ire value 2.015631] h = [20 2.015631] h = [40.31262] h = 28 h 2. standard: pal. to add ? ire brightness level write 72 h into the brightness control register: [| ire value | 2.015631] = [7 2.015631] = [14.109417] = 0001110 b [0001110] into two? complement = 1110010 b = 72 h bcr6 ? bcr0 brightness value bcr7 zero must be written to this bit bcr7 bcr6 bcr5 bcr4 bcr3 bcr2 bcr1 bcr0 100 ire 0 ire +7.5 ire ?7.5 ire ntsc without pedestal no setup value added positive setup value added write to brightness control register: 12 h negative setup value added write to brightness control register: 6e h figure 75. brightness control register
rev. b adv7190/adv7191 C40C sharpness control register (pr) (address (sr5?r0) = 22h) t he sharpness response register is an 8-bit-wide register. the four msbs are set to 0. the four lsbs are written to in order to select a desired ?ter response. figure 76 shows the operation under control of this register. pr bit description sharpness response value (pr3?r0) these four bits are used to select the desired luma ?ter response. the option of twelve responses is given supporting a gain boost/ attenuation in the range ? db to +4 db. the value 12 (1100) written to these four bits corresponds to a boost of +4 db while the value 0 (0000) corresponds to ? db. for normal operation these four bits are set to 6 (0110). n ote: luma filter select has to be set to extended mode and sharpness filter enable control has to be enabled for settings in the sharpness control register to take effect (mr02?4 = 100; mr74 = 1). see internal filter response section. reserved (pr4?r7) a logic 0 must be written to these bits. pr3 ? pr0 sharpness response value zero must be written to these bits pr7 ? pr4 pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 f igure 76. sharpness control register d nr registers 2? (dnr 2?nr 0) ( address (sr5?r0) = 23h?5h) the digital noise reduction registers are three 8-bit-wide registers. they are used to control the dnr processing. see digital noise reduction section. coring gain border (dnr00?nr03) these four bits are assigned to the gain factor applied to border areas. in dnr mode the range of gain values is 0?, in increments of 1/ 8. this factor is applied to the dnr ?ter output which lies below the set threshold range. the result is then subtracted from the original signal. in dnr sharpness mode the range of gain values is 0?.5 in increments of 1/16. this factor is applied to the dnr ?ter output which lies above the threshold range. the result is added to the original signal. coring gain data (dnr04?nr07) these four bits are assigned to the gain factor applied to the luma data inside the mpeg pixel block. in dnr mode the range of gain values is 0?, in increments of 1 /8. this factor is applied to the dnr ?ter output which lies below the set threshold range. the result is then subtracted f rom the original signal. in dnr sharpness mode the range of gain values is 0?.5, in increments of 1/16. this factor is applied to the dnr ?ter output which lies above the threshold range. the result is added to the original signal. figures 77 and 78 show the various operations under the con trol of dnr register 0. dnr07 dnr06 dnr05 dnr04 dnr03 dnr02 dnr01 dnr00 coring gain data dnr dnr dnr dnr 07 06 05 04 0 0 0 0 0 0001 1/16 0010 2/16 0011 3/16 0100 4/16 0101 5/16 0110 6/16 0111 7/16 1000 8/16 coring gain border dnr dnr dnr dnr 03 02 01 00 0 0 0 0 0 0001 1/16 0010 2/16 0011 3/16 0100 4/16 0101 5/16 0110 6/16 0111 7/16 1000 8/16 figure 77. dnr register 0 in sharpness mode coring gain data dnr dnr dnr dnr 07 06 05 04 0 0 0 0 0 0001 1/8 0010 2/8 0011 3/8 0100 4/8 0101 5/8 0110 6/8 0111 7/8 1000 1 coring gain border dnr dnr dnr dnr 03 02 01 00 0 0 0 0 0 0001 1/8 0010 2/8 0011 3/8 0100 4/8 0101 5/8 0110 6/8 0111 7/8 1000 1 dnr07 dnr06 dnr05 dnr04 dnr03 dnr02 dnr01 dnr00 figure 78. dnr register 0 in dnr mode d nr1 bit description d nr threshold (dnr10?nr15) these six bits are used to de?e the threshold value in the range of 0 to 63. the range is an absolute value. border area (dnr16) in setting dnr16 to a logic 1 the block transition area can be de?ed to consist of four pixels. if this bit is set to a logic 0 the b order transition area consists of two pixels, where one pixel refers to two clock cycles at 27 mhz. block size control (dnr17) t his bit is used to select the size of the data blocks to be processed ( see figure 79). setting the block size control function to a logic 1 de?es a 16 16 pixel data block, a logic 0 de?es an 8 8 pixel data block, where one pixel refers to two clock cycles at 27 mhz. 720 485 pixels (ntsc) 2 pixel border data 8 8 pixel block 8 8 pixel block figure 79. mpeg block diagram
rev. b adv7190/adv7191 C41C d nr2 bit description d nr input select (dnr20?nr22) three bits are assigned to select the ?ter that is applied to the i ncoming y data. the signal that lies in the passband of the selected ?ter is the signal that will be dnr processed. figure 81 shows the ?ter responses selectable with this control. frequency ? mhz 1 0.4 0.6 0.2 01 magnitude ? db 234 6 5 0.8 0 filter d filter c filter a filter b f igure 81. filter response of filters selectable dnr mode control (dnr23) this bit controls the dnr mode selected. a logic 0 selects dnr mode, a logic 1 selects dnr sharpness mode. d nr works on the principle of de?ing low amplitude, high- frequency signals as probable noise and subtracting this noise f rom the original signal. in dnr mode, it is possible to subtract a fraction of the signal that lies below the set threshold, assumed to be noise, from t he original signal. the threshold is set in dnr register 1. wh en dnr sharpness mode is enabled it is possible to add a fraction of the signal that lies above the set threshold to the original signal, since this data is assumed to be valid data and not noise. the overall effect being that the signal will be boosted (similar to using extended ssaf filter). filter output < threshold ? gain control block size control border area block offset gain coring gain data coring gain border filter block filter output > threshold dnr out main signal path y data input noise signal path subtract signal in threshold range from original signal dnr mode filter output > threshold ? gain control block size control border area block offset gain coring gain data coring gain border filter block filter output < threshold dnr out main signal path y data input noise signal path add signal above threshold range to original signal dnr sharpness mode figure 82. block diagram for dnr mode and dnr sharp- ness mode block offset (dnr24?nr27) four bits are assigned to this control which allows a shift of the data block of 15 pixels maximum. consider the coring gain posi- tions ?ed. the block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data. o x x x x x x o o x x x x x x o apply data coring gain apply border coring gain offset caused by variations in input timing dnr27 ? dnr24 = 01 hex o x x x x x x o o x x x x x x o o x x x x x x o o x x x x x x o figure 83. dnr27Cdnr24, block offset control dnr17 dnr16 dnr15 dnr14 dnr13 dnr12 dnr11 dnr10 dnr threshold dnr dnr dnr dnr dnr dnr 15 14 13 12 11 10 0 0 0 0 0 0 0 0000011 ??????? ??????? ??????? 11111062 11111163 02 pixels 14 pixels dnr16 border area 08 pixels 1 16 pixels dnr17 block size control figure 80. dnr register 1
rev. b adv7190/adv7191 C42C g amma correction registers 0?3 (gamma correction 0?3) ( address (sr5?r0) = 26h?2h) the gamma correction registers are fourteen 8-bit-wide registers. they are used to program the gamma correction curves a and b. g amma correction is applied to compensate for the nonlinear relationship between signal input and brightness level output (as perceived on the crt). it can also be applied wherever nonlin- ear processing is used. gamma correction uses the function: signal out = (si gnal in ) g where g = g amma power factor ga mma correction is performed on the luma data only. the user has the choice to use two different curves, curve a, or curve b. at any one time only one of these curves can be used. t he response of the curve is programmed at seven prede?ed locations. in changing the values at these locations the gamma curve can be modi?d. between these points linear interpolation is used to generate intermediate values. considering the curve to have a total length of 256 points, the seven locations are at: 32, 64, 96, 128, 160, 192, and 224. values at location 0, 16, 240, and 255 are ?ed and cannot be changed. for the length of 16 to 240 the gamma correction curve has to be calculated as below: y = x g where y = gamma corrected output x = linear input signal g = gamma power factor to program the gamma correction registers, the seven values for y have to be calculated using the following formula: y n = [ x ( n 16) /(240?6) ] g (240?6) + 16 where x ( n- 16) = value for x along x-axis y n = value for y along the y-axis, which has to be written into the gamma correction register n = 32, 64, 96, 128, 160, 192, or 224 example: y 32 = [(16/224) 0 .5 224] + 16 = 76 * y 64 = [(48/224) 0 .5 224] + 16 =120 * y 96 = [(80/224) 0 .5 224] + 16 = 150 * y 128 = [(112/224) 0 .5 224] + 16 = 174 * * rounded to the nearest integer. the above will result in a gamma curve shown below, assuming a ramp signal as an input. 250 200 150 100 50 0 300 250 200 150 100 50 300 signal output signal input 0.5 gamma correction block output to a ramp input gamma?corrected amplitude 050 100 150 200 250 location figure 85. signal input (ramp) and signal output for gamma 0.5 250 200 150 100 50 0 300 signal outputs signal input 0.5 gamma correction block output to a ramp input for various gamma values gamma?corrected amplitude 050 100 150 200 250 location 0.3 1.5 1.8 figure 86. signal input (ramp) and selectable gamma output curves the gamma curves shown above are examples only, any user- de?ed curve is acceptable in the range of 16?40. dnr27 dnr26 dnr25 dnr24 dnr23 dnr22 dnr21 dnr20 block offset dnr dnr dnr dnr 27 26 25 24 0000 0 pixel offset 0001 1 pixel offset 0010 2 pixel offset ???? ? ???? ? ???? ? 110113 pixel offset 111014 pixel offset 111115 pixel offset dnr input select dnr dnr dnr 22 21 20 00 1 filter a 01 0 filter b 01 1 filter c 10 0 filter d 0 dnr mode 1 dnr sharpness mode dnr23 dnr mode control figure 84. dnr register 2
rev. b adv7190/adv7191 C43C brightness detect register ( address (sr5?r0) = 34h) t he brightness detect register is an 8-bit-wide register used only to read back data in order to monitor the brightness/darkness of th e incom ing video data on a ?ld-by-?ld basis. the brightness information is read from the i 2 c and based on this information, th e color controls or the gamma correction controls may be adjusted. the luma data is monitored in the active video area only. the average brightness i 2 c register is updated on the falling edge of every vsync signal. o utput clock register (ocr 9?) ( address (sr4?r0) = 35h) t he output clock register is an 8-bit-wide register. figure 87 shows the various operations under the cont rol of this register. o cr bit description reserved (ocr00) a logic 0 must be written to this bit. clkout pin control (ocr01) this bit enables the clkout pin when set to 1 and, therefore, outputs a 54 mhz clock generated by the internal pll. the pll and 4 oversampling have to be enabled for this control to take effect (mr61 = 0; mr16 = 1). reserved (ocr02?3) a logic 0 must be written to these bits. reserved (ocr04?6) a logic 1 must be written to these bits. reserved (ocr07) a logic 0 must be written to this bit. ocr07 ocr06 ocr05 ocr04 ocr03 ocr02 ocr01 ocr00 ocr07 zero must be written to this bit clkout pin control 0 ensabled 1 disabled ocr01 ocr06 ? ocr04 one must be written to these bits ocr03 ? ocr02 zero must be written to these bits ocr00 zero must be written to this bit figure 87. output clock register (ocr)
rev. b adv7190/adv7191 C44C appendix 1 board design and layout considerations the adv7190/adv7191 is a highly integrated circuit co ntain- ing both preci sion analog and high-speed digital circuitry. it has been designed to minimize interference effects on the integ- rity of the analog circuitry by the high-speed digital circuitry. it is imperative that these same design and layout techniques be a pplied to the system -level design such that high-speed, accurate performance is achieved. the recommended analog circuit lay- out shows the analog interface between the device and monitor. the layout should be optimized for lowest noise on the adv7190/ adv7191 power and ground lines by shielding the digital inputs and providing good decoupling. the lead length between groups of v aa and agnd pins should by minimized in order to mini- mi ze inductive ringing. ground planes the ground plane should encompass all adv7190/adv7191 g round pins, voltage reference circuitry, power supply bypass cir- cuitry for the adv7190/adv7191, the analog output traces, and all the digital signal traces leading up to the adv7190/adv7191. power planes t he adv7190/adv7191 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (v aa ). this power plane should be connected to the regular pcb power plane (v cc ) at a single point through a ferrite bead. this bead should be located within three inches of the adv7190/adv7191. the metallization gap separating device power plane and board power plane should be as narrow as possible to minimize the obstruction to the flow of heat from the device into the gen- eral board. the pcb power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all adv7190/adv7191 power pins and voltage reference circuitry. plane-to-plane noise coupling can be reduced by ensuring that portions of the regular pcb power and ground planes do not overlay portions of the analog power plane, unless they can be arranged so the plane-to-plane noise is common-mode. supply decoupling for o ptimum performance, bypass capacit ors should be inst alled using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. best performance is obtained wi th 0.1 m f ceramic capacitor decoupling. each group of v aa pins on the adv7190/adv7191 must have at least one 0.1 m f decoupling capacitor to agnd. these capacitors should be placed as close as possible to the device. it is important to note that while the adv7190/adv7191 contains circuitry to reject power supply noise, this rejection de creases with frequency. if a high-frequency switching power s upply is used, the designer should pay close attention to reducing power supply noise and consider using a three-terminal voltage regulator for supplying power to the analog power plane. digital signal interconnect the digital inputs to the adv7190/adv7191 should be isolated as m uch as possible from the analog outputs and other analog circuitry. a lso, these input signals should not overlay the analog power plane. d ue to the high clock rates involved, long clock lines to the adv7190/adv7191 should be avoided to reduce noise pickup. any active termination resistors for the digital inputs should be connected to the regular pcb power plane (v cc ), and not the analog power plane. analog signal interconnect the adv7190/adv7191 should be located as close as possible to the output connectors to minimize noise pickup and reflec- tions due to impedance mismatch. the video output signals should overlay the ground plane, and n ot the analog power plane, to maximize the high frequency power sup ply rejection. digital inputs, especially pixel data inputs and clocking signals s hould never overlay any of the analog signal circuitry and should be kept as far away as possible. for best performance, the outputs should each have a 300 w load resistor connected to agnd. these resistors should be placed as close as possible to the adv7190/adv7191 so as to mini- mize reflections. t he adv7190/adv7191 should have no inputs left floating. any inputs that are not required should be tied to ground.
rev. b adv7190/adv7191 C45C appendix 1 board layout 0.1 f 5v (v aa ) comp2 300 5k 5v (v aa ) 5k mpu bus 5v (v aa ) 4.7k 5v (v aa ) power supply decoupling for each power supply group agnd alsb hsync vsync blank reset clkin r set1 sda scl dac a v aa v ref p0 p15 screset/rtc/tr adv7190/ adv7191 unused inputs should be grounded dac b 100 5v (v aa ) ttx ttxreq 0.1 f comp1 vso /clamp pal_ntsc dac c dac d dac e dac f r set2 27mhz clock (same clock as used by mpeg2 decoder) cso_hso 4.7k 4.7 f 6.3v 17, 25, 29, 38, 43, 54, 63 300 300 300 300 300 5v (v aa ) 100 1.2k 1.2k 18, 24, 26, 33, 39, 42, 55, 64 10nf 0.1 f 5v (v aa ) connect dac outputs to optional output filter and buffer circuit clkout figure 88. recommended analog circuit layout
rev. b adv7190/adv7191 C46C appendix 2 closed captioning the adv7190/adv7191 supports closed captioning con forming to the standard television synchronizing waveform for color transmission. closed captioning is transmitted during the blanked active line time of line 21 of the odd ?lds and line 284 of even ?lds. c losed captioning consists of a seven-cycle sinusoidal burst tha t is frequency and phase locked to the caption data. after the c lock run-in signal, the blanking level is held for two data bits and is followed by a logic level 1 start bit. sixteen bits of data follow the start bit. these consist of two eight-bit bytes, seven data bits, and one odd parity bit. the data for these bytes is stored in c losed captioning data registers 0 and 1. t he adv7190/adv7191 also supports the extended closed captioning operation that is active during even ?lds and is encoded on scan line 284. the data for this operation is stored in closed captioning extended data registers 0 and 1. al l clock run-in signals and timing to support closed captioning on lines 21 and 284 are generated automatically by the adv7190/ adv7191 all pixel inputs are ignored during lines 21 and 284 if closed captioning is enabled. fcc code of federal regulations (cfr) 47 section 15.119 and eia608 describe the closed captioning information for lines 21 and 284. the adv7190/adv7191 uses a single buffering method. this means that the closed captioning buffer is only one byte deep, therefore there will be no frame delay in outputting the closed captioning data, unlike other two byte deep buffering systems. the data must be loaded one line before (line 20 or line 283) it is outputted on line 21 and line 284. a typical implementation of this method is to use vsync to interrupt a microprocessor, which in turn, will load the new data (two bytes) every ?ld. if no ne w data is required for transmission, 0s must be inserted in both data registers, this is called nulling. it is also im port ant to load control codes, all of which are double bytes on line 21, or a tv w ill not recognize them. if there is a mes- sage like hello world, which has an odd number of characters, it is important to pad it out to even in order to get end of caption 2-byte control code to land in the same ?ld. 12.91 s 10.003 s 33.764 s 50 ire 40 ire frequency = f sc = 3.579545mhz amplitude = 40 ire reference color burst (9 cycles) 7 cycles of 0.5035 mhz (clock run-in) 10.5 0.25 s two 7-bit + parity ascii characters (data) 27.382 s s t a r t p a r i t y p a r i t y d0?d6 d0?d6 byte 0 byte 1 figure 89. closed captioning waveform (ntsc)
rev. b adv7190/adv7191 C47C appendix 3 copy generation management system (cgms) t he adv7190/adv7191 supports copy generation management system (cgms) conforming to the standard. cgms data is transmitted on line 20 of the odd ?lds and line 283 of even ?lds. bits c/w05 and c/w06 control whether or not cgms data is outputed on odd and even ?lds. cgms data can o nly be transmitted when the adv7190/adv7191 is con?ured in ntsc mode. the cgms data is 20 bits long, the function of each of these bits is as shown below. the cgms data is preceded by a reference pulse of the same amplitude and duration as a cgms bit, see figure 94. these bits are output from the con?u- ration registers in the following order: c/w00 = c16, c/w01 = c17, c/w02 = c18, c/w03 = c19, c/w10 = c8, c/w11 = c9, c/w12 = c10, c/w13 = c11, c/w14 = c 12, c/w15 = c 13, c/w16 = c14, c/w17 = c15, c/w20 = c0, c/w21 = c1, c/w22 = c2, c/w23 = c3, c/w24 = c4, c/w25 = c5, c/w26 = c6, c/w27 = c7. if the bit c/w04 is set to a logic 1, the last six bits c19?14 which comprise the 6-bit crc check sequence are calculated automatically on the adv7190/adv7191 based on the lower 14 bits (c0?13) of the data in the data registers and output with the r emaining 14-bits to form the complete 20-bits of the cgms data. the calculation of the crc sequence is based on the pol ynomial x 6 + x + 1 wi th a preset value of 111111. if c/w04 is set to a logic 0, all 20 bits (c0?19) are output directly from the cgms registers (no crc calculated, must be calculated by the user). function of cgms bits word 0 ?6 bits word 1 ?4 bits word 2 ?6 bits crc ?6 bits crc polynomial = x 6 + x + 1 (preset to 111111) word 0 1 0 b1 aspect ratio 16:9 4:3 b2 display format letterbox normal b3 unde?ed word 0 b4, b5, b6 identi?ation information about video and other signals (e.g., audio) word 1 b7, b8, b9, identi?ation signal incidental to word 0 b10 word 2 b11, b12, identi?ation signal and information b13, b14 incidental to word 0 crc sequence 49.1 s 0.5 s 11.2 s 2.235 s 20ns ref c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 100 ire 70 ire 0 ire ?40 ire figure 90. cgms waveform diagram
rev. b adv7190/adv7191 C48C appendix 4 wide screen signaling (wss) the adv7190/adv7191 supports wide screen signaling (wss) c onforming to the standard. wss data is transmitted on line 23. wss data can only be transmitted when the adv7190/adv7191 is con? ured in pal mode. the wss data is 14-bits long, the function of each of these bits is as shown below. the wss data is preceded by a run-in sequence and a start code, see figure 91. the bits are output from the con?uration registers in the follow ing order: c/w20 = w0, c/w21 = w1, c/w22 = w2, c/w23 = w3, c/w24 = w4, c/w25 = w5, c/w26 = w6, c/w27 = w7, c/w10 = w8, c/w11 = w9, c/w12 = w10, c/w13 = w11, c/w14 = w12, c/w15 = w13. if the bit c/ w0 7 is set to a l ogic 1, it enables the wss data to be trans- mitted on line 23. the latter portion of line 23 (42.5 m s from t he falling edge of hsync ) is available for the insertion of video. function of cgms bits bit 0?it 2 aspect ratio/format/position bit 3 is odd parity check of bit 0?it 2 aspect b0, b1, b2, b3 ratio format position 00 01 4:3 full format nonapplicable 10 00 14:9 letterbox center 01 00 14:9 letterbox top 11 01 16:9 letterbox center 00 10 16:9 letterbox top 10 11 >16:9 letterbox center 01 11 14:9 full format center 11 10 16:9 nonapplicable nonapplicable b4 0c amera mode 1 film mode b5 0 standard coding 1m otion adaptive color plus b6 0n o helper 1m odulated helper b7 reserved b9 b10 00 no open subtitles 10 subtitles in active image area 01 subtitles out of active image area 11 reserved b11 0n o surround sound information 1 surround sound mode b12 reserved b13 reserved w0 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 500mv run-in sequence start code active video 38.4 s 42.5 s 11.0 s figure 91. wss waveform diagram
rev. b adv7190/adv7191 C49C appendix 5 teletext insertion time, t pd , is the time needed by the adv7190/adv7191 to interpolate input data on ttx and insert it onto the cvbs or y outputs, such that it appears t synttxout = 10.2 m s after the leading edge of the horizontal signal. time, ttx del , is the pipe line delay time by the source that is gated by the ttxreq signal in order to deliver ttx data. with the programmability that is offered with ttxreq signal on the rising/falling edges, the ttx data is always inserted at the correct position of 10.2 m s after the leading edge of h orizontal sync pulse, which enables a source interface with variable pipe- line delays. the width of the ttxreq signal must always be maintained so it allows the insertion of 360 (in order to comply with the teletext standard pal-wst) teletext bits at a text data rate of 6.9375 mbits/s. this is achieved by setting tc03?c00 to 0. the insertion window is not open if the teletext enable bit (mr33) is set to 0. teletext protocol the relationship between the ttx bit clock (6.9375 mhz) and the system clock (27 mhz) for 50 hz is given as follows: (27 mhz /4) = 6.75 mhz (6.9375 10 6 /6.75 10 6 = 1.027777 thus 37 ttx bits correspond to 144 clocks (27 mhz), each bit has a width of almost four clock cycles. the adv7190/adv7191 uses an internal sequencer and variable phase inte rpolation ?ter to minimize the phase jitter and thus generate a bandlimited signal w hich can be output on the cvbs and y outputs. at the ttx input the bit duration scheme repeats after every 37 ttx bits or 144 clock cycles. the protocol requires that ttx bits 10, 19, 28, 37 are carried by three clock cycles, all other bits by four clock cycles. after 37 ttx bits, the next bits with three clock cycles are bits 47, 56, 65, and 74. this scheme holds for all following cycles of 37 ttx bits, until all 360 ttx b its are completed. all teletext lines are implemented in the same way. individual control of teletext lines are controlled by teletext setup registers. address & data run-in clock teletext vbi line 45 bytes (360 bits) ? pal figure 92. teletext vbi line programmable pulse edges t pd t pd cvbs/y hsync ttxreq ttx data t synttxout = 10.2 s t pd = pipeline delay through adv7190/adv7191 ttx del = ttxreq to ttx (programmable range = 4 bits [0?15 clock cycles]) ttx del ttx st t synttxout 10.2 s figure 93. teletext functionality diagram
rev. b adv7190/adv7191 C50C appendix 6 optional output filter if an output ?ter is required for the cvbs, yuv, chroma, and rgb outputs of the adv7190/adv7191, the ?ter in figure 94 can be used in 2 oversampling mode. figure 96 shows a filter that can be used in 4 oversampling mode. the plot of the ?ter characteristics are shown in figures 95 and 97. an output ?ter is not required if the outputs of the adv7190/adv7191 are connected to most analog monitors, or tvs; however, if the output signals are applied to a system where sampling is used (e.g., digital tvs), a ?ter is required to prevent aliasing. 22 h 68pf 22 h filter i/p filter o/p 22pf 56pf 6.8 h 600 600 figure 94. output filter for 2 oversampling mode 100k ?60 ?50 0 100m ?70 magnitude ? db frequency ? hz 1.0m 10m ?40 ?30 ?20 ?10 figure 95. output filter plot for 2 oversampling filter 10 h 68pf 22 h filter i/p filter o/p 27pf 600 600 figure 96. output filter for 4 oversampling mode 100k ?63 ?49 ?42 100m ?70 magnitude ? db frequency ? hz 1.0m 10m ?56 ?35 ?28 ?21 ?14 ?7 0 figure 97. output filter plot for 4 oversampling filter 27.0 40.5 54.0 13.5 6.75 frequency ? mhz 2 filter requirements 4 filter requirements figure 98. output filter requirements in 4 oversampling mode
rev. b adv7190/adv7191 C51C appendix 7 dac buffering e xternal buffering is needed on the adv7190 /adv7191 dac outputs. the con?uration in figure 99 is recommended. when calculating absolute output full-scale current and voltage use the following equations: v out = i out r load i out = ( v ref k )/ r set k = 4.2146 constant , v ref = 1.235 v adv7190/adv7191 v ref pixel port v aa output buffer dac a cvbs chroma g luma b r 1.2k r set1 dac b dac c dac d dac e dac f digital core 1.2k r set2 output buffer output buffer output buffer output buffer output buffer figure 99. output dac buffering con?guration output to tv monitor input/ optional filter o/p +v cc ad8051 ?v cc 2 1 5 3 4 figure 100. recommended dac output buffer using an op amp
rev. b adv7190/adv7191 C52C appendix 8 recommended register values ntsc (f sc = 3.5795454 mhz) address data 00hex mode register 0 10hex 01hex mode register 1 3fhex 02hex mode register 2 62hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 08hex mode register 8 04hex 09hex mode register 9 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 16hex 0dhex subcarrier frequency register 1 7chex 0ehex subcarrier frequency register 2 f0hex 0fhex subcarrier frequency register 3 21hex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness response register 00hex 23hex dnr 0 44hex 24hex dnr 1 20hex 25hex dnr 2 00hex 35hex output clock register 70hex pal b, d, g, h, i (f sc = 4.43361875 mhz) address data 00hex mode register 0 11hex 01hex mode register 1 3fhex 02hex mode register 2 62hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 08hex mode register 8 04hex 09hex mode register 9 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 cbhex 0dhex subcarrier frequency register 1 8ahex 0ehex subcarrier frequency register 2 09hex 0fhex subcarrier frequency register 3 2ahex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness response register 00hex 23hex dnr0 44hex 24hex dnr1 20hex 25hex dnr2 00hex 35hex output clock register 70hex the adv7190/adv7191 registers can be set depending on the user standard required. the following examples give the various register formats for several video standards.
rev. b adv7190/adv7191 C53C pal n (f sc = 4.43361875 mhz) address data 00hex mode register 0 13hex 01hex mode register 1 3fhex 02hex mode register 2 62hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 08hex mode register 8 04hex 09hex mode register 9 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 cbhex 0dhex subcarrier frequency register 1 8ahex 0ehex subcarrier frequency register 2 09hex 0fhex subcarrier frequency register 3 2ahex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness response register 00hex 23hex dnr 0 44hex 24hex dnr 1 20hex 25hex dnr 2 00hex 35hex output clock register 70hex pal 60 (f sc = 4.43361875 mhz) address data 00hex mode register 0 12hex 01hex mode register 1 3fhex 02hex mode register 2 62hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 08hex mode register 8 04hex 09hex mode register 9 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 cbhex 0dhex subcarrier frequency register 1 8ahex 0ehex subcarrier frequency register 2 09hex 0fhex subcarrier frequency register 3 2ahex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness response register 00hex 23hex dnr 0 44hex 24hex dnr 1 20hex 25hex dnr 2 00hex 35hex output clock register 70hex
rev. b adv7190/adv7191 C54C pal m (f sc = 3.57561149 mhz) address data 00hex mode register 0 12hex 01hex mode register 1 3fhex 02hex mode register 2 62hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 08hex mode register 8 04hex 09hex mode register 9 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 a3hex 0dhex subcarrier frequency register 1 efhex ehex subcarrier frequency register 2 e6hex 0fhex subcarrier frequency register 3 21hex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex address data 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness response register 00hex 23hex dnr 0 44hex 24hex dnr 1 20hex 25hex dnr 2 00hex 35hex output clock register 70hex
rev. b adv7190/adv7191 C55C power-on reset reg values (pal_ntsc = 0, ntsc selected) address data 00hex mode register 0 00hex 01hex mode register 1 07hex 02hex mode register 2 08hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 08hex mode register 8 00hex 09hex mode register 9 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 16hex 0dhex subcarrier frequency register 1 7chex 0ehex subcarrier frequency register 2 f0hex 0fhex subcarrier frequency register 3 21hex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness response register 00hex 23hex dnr 0 00hex 24hex dnr 1 00hex 25hex dnr 2 00hex 26hex gamma 0 xxhex 27hex gamma 1 xxhex 28hex gamma 2 xxhex 29hex gamma 3 xxhex 2ahex gamma 4 xxhex 2bhex gamma 5 xxhex 2chex gamma 6 xxhex 2dhex gamma 7 xxhex 2ehex gamma 8 xxhex 2fhex gamma 9 xxhex 30hex gamma 10 xxhex 31hex gamma 11 xxhex 32hex gamma 12 xxhex 33hex gamma 13 xxhex 34hex brightness detect register xxhex 35hex output clock register 72hex power-on reset reg values (pal_ntsc = 1, pal selected) address data 00hex mode register 0 01hex 01hex mode register 1 07hex 02hex mode register 2 08hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 08hex mode register 8 00hex 09hex mode register 9 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 cbhex 0dhex subcarrier frequency register 1 8ahex 0ehex subcarrier frequency register 2 09hex 0fhex subcarrier frequency register 3 2ahex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness response register 00hex 23hex dnr 0 00hex 24hex dnr 1 00hex 25hex dnr 2 00hex 26hex gamma 0 xxhex 27hex gamma 1 xxhex 28hex gamma 2 xxhex 29hex gamma 3 xxhex 2ahex gamma 4 xxhex 2bhex gamma 5 xxhex 2chex gamma 6 xxhex 2dhex gamma 7 xxhex 2ehex gamma 8 xxhex 2fhex gamma 9 xxhex 30hex gamma 10 xxhex 31hex gamma 11 xxhex 32hex gamma 12 xxhex 33hex gamma 13 xxhex 34hex brightness detect register xxhex 35hex output clock register 72hex power-on reset register values
rev. b adv7190/adv7191 C56C appendix 9 ntsc waveforms (with pedestal) 130.8 ire 100 ire 7.5 ire 0 ire ?40 ire peak composite ref white black level sync level blank level 714.2mv 1268.1mv 1048.4mv 387.6mv 334.2mv 48.3mv figure 101. ntsc composite video levels 100 ire 7.5 ire 0 ire ?40 ire ref white black level sync level blank level 714.2mv 1048.4mv 387.6mv 334.2mv 48.3mv figure 102. ntsc luma video levels 650mv 335.2mv 963.8mv 0mv peak chroma blank/black level 286mv (p-p) 629.7mv (p-p) peak chroma figure 103. ntsc chroma video levels 100 ire 7.5 ire 0 ire ?40 ire ref white black level sync level blank level 720.8mv 1052.2mv 387.5mv 331.4mv 45.9mv figure 104. ntsc rgb video levels
rev. b adv7190/adv7191 C57C ntsc waveforms (without pedestal) 130.8 ire 100 ire 0 ire ?40 ire peak composite ref white sync level blank/black level 714.2mv 1289.8mv 1052.2mv 338mv 52.1mv figure 105. ntsc composite video levels 100 ire 0 ire ?40 ire ref white sync level blank/black level 714.2mv 1052.2mv 338mv 52.1mv figure 106. ntsc luma video levels 650mv 283mv 978mv 0mv peak chroma blank/black level 307mv (p-p) peak chroma 694.9mv (p-p) figure 107. ntsc chroma video levels 100 ire 0 ire ?40 ire ref white sync level blank/black level 715.7mv 1052.2mv 336.5mv 51mv figure 108. ntsc rgb video levels
rev. b adv7190/adv7191 C58C pal waveforms 1284.2mv 1047.1mv 350.7mv 50.8mv peak composite ref white sync level blank/black level 696.4mv figure 109. pal composite video levels 1047mv 350.7mv 50.8mv ref white sync level blank/black level 696.4mv figure 110. pal luma video levels 650mv 318mv 990mv 0mv peak chroma blank/black level 300mv (p-p) 672mv (p-p) peak chroma figure 111. pal chroma video levels 1050.2mv 351.8mv 51mv ref white sync level blank/black level 698.4mv figure 112. pal rgb video levels
rev. b adv7190/adv7191 C59C uv waveforms betacam level 0mv 171mv 334mv 505mv 0mv 171mv 334mv 505mv white yellow cyan green magenta red blue black figure 113. ntsc 100% color bars, no pedestal u levels betacam level 0mv 158mv 309mv 467mv 0mv ?158mv ?309mv ?467mv white yellow cyan green magenta red blue black figure 114. ntsc 100% color bars with pedestal u levels smpte level 0mv 118mv 232mv 350mv 0mv ?118mv ?232mv ?350mv white yellow cyan green magenta red blue black figure 115. pal 100% color bars u levels betacam level 0mv 82mv 423mv 505mv 0mv ?82mv ?505mv ?423mv white yellow cyan green magenta red blue black figure 116. ntsc 100% color bars, no pedestal v levels betacam level 0mv 76mv 391mv 467mv 0mv ?76mv ?467mv ?391mv white yellow cyan green magenta red blue black figure 117. ntsc 100% color bars with pedestal v levels smpte level 0mv 57mv 293mv 350mv 0mv ?57mv ?350mv ?293mv white yellow cyan green magenta red blue black figure 118. pal 100% color bars v levels
rev. b adv7190/adv7191 C60C 0.6 0.4 0.2 0.0 0.2 l608 0.0 10.0 20.0 30.0 40.0 50.0 60.0 microseconds noise reduction: 0.00 db apl = 39.1% precision mode off sound-in-sync off 625 line pal no filtering synchronous sync = source slow clamp to 0.00 v at 6.72 s frames selected: 1 2 3 4 volts figure 119. 100/0/75/0 pal color bars microseconds apl needs sync = source! precision mode off sound-in-sync off 625 line pal no filtering synchronous sync = a slow clamp to 0.00 v at 6.72 s frames selected: 1 0.5 0.0 l575 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 volts figure 120. 100/0/75/0 pal color bars luminance output waveforms
rev. b adv7190/adv7191 C61C apl needs sync = source! precision mode off sound-in-sync off 625 line pal no filtering synchronous sync = a slow clamp to 0.00 v at 6.72 s frames selected: 1 0.5 0.0 ?0.5 10.0 30.0 40.0 50.0 60.0 20.0 microseconds l575 volts no bruch signal figure 121. 100/0/75/0 pal color bars chrominance apl = 44.6% precision mode off 525 line ntsc no filtering synchronous sync = a slow clamp to 0.00 v at 6.72 s frames selected: 1 2 microseconds 0.5 0.0 ?50.0 50.0 100.0 ire:flt volts f1 l76 0.0 10.0 20.0 30.0 40.0 50.0 60.0 0.0 figure 122. 100/7.5/75/7.5 ntsc color bars
rev. b adv7190/adv7191 C62C noise reduction: 15.05db apl = 44.7% precision mode off 525 line ntsc no filtering synchronous sync = source slow clamp to 0.00 v at 6.72 s frames selected: 1 2 microseconds 10.0 20.0 30.0 40.0 50.0 60.0 0.6 0.4 0.2 0.0 ?0.2 50.0 0.0 ire:flt volts f2 l238 100.0 figure 123. 100/7.5/75/7.5 ntsc color bars luminance noise reduction: 15.05db apl needs sync = source! precision mode off 525 line ntsc no filtering synchronous sync = b slow clamp to 0.00 v at 6.72 s frames selected: 1 2 microseconds 0.0 10.0 20.0 30.0 40.0 50.0 60.0 0.4 0.2 0.0 ?0.2 ?0.4 volts 50.0 ?50.0 f1 l76 ire:flt figure 124. 100/7.5/75/7.5 ntsc color bars chrominance
rev. b adv7190/adv7191 C63C parade smpte/ebu pal mv y(a) mv pb(b) mv pr(c) 700 600 500 400 300 200 100 0 ?100 ?200 ?300 250 200 150 100 50 ?50 ?100 ?150 ?200 ?250 0 250 200 150 100 50 ?50 ?100 ?150 ?200 ?250 0 figure 125. pal yuv parade plot mv green (a) mv blue (b) mv red (c) 700 600 500 400 300 200 100 0 ?100 ?200 ?300 700 600 500 400 300 200 100 0 700 600 500 400 300 200 100 0 ?100 ?200 ?300 ?100 ?200 ?300 figure 126. pal rgb waveforms
rev. b adv7190/adv7191 C64C video measurement plots gray yellow cyan green magenta red blue black 0 50 100 luminance level (ire) 99.6 69.0 55.9 48.1 36.3 28.3 15.7 7.7 gray yellow cyan green magenta red blue black 0.0 62.1 87.6 81.8 81.8 87.8 62.1 0.0 chrominance level (ire) 0 50 100 gray yellow cyan green magenta red blue black 400 200 0 167.3 283.8 240.9 60.80 103.6 347.1 chrominance phase (degree) average 32 32 color bar (ntsc) field = 1 line = 21 wfm fcc color bar figure 127. ntsc color bar measurement gray yellow cyan green magenta red blue black 0 500 1000 luminance level (mv) 695.7 464.8 366.6 305.7 217.3 156.4 61.2 ?0.4 gray yellow cyan green magenta red blue black 0 500 1000 0.0 474.4 669.1 623.5 624.7 669.6 475.2 0.0 chrominance level (mv) gray yellow cyan green magenta red blue black 400 200 0 100 300 166.7 283.3 240.4 60.4 103.2 346.7 chrominance phase (degree) average 32 32 color bar (pal) line = 570 wfm color bar figure 128. pal color bar measurement
rev. b adv7190/adv7191 C65C dg dp (ntsc) wfm field = 1, line = 21 mod 5 step 1 st ?2.5 ?1.5 ?0.5 0.5 1.5 2.5 2 nd 3 rd 4 th 5 th 6 th 0.00 0.21 0.02 0.07 0.27 0.08 diifferential gain (percent) min = 0.00, max = 0.27, p-p/max = 0.27 1 st ?2.5 ?1.5 ?0.5 0.5 1.5 2.5 2 nd 3 rd 4 th 5 th 6 th 0.00 0.10 0.12 0.15 0.13 0.10 differential phase (degree) min = 0.00, max = 0.20, pk-pk = 0.20 average 32 32 figure 129. ntsc dg dp measurement 89 91 93 95 97 99 101 103 105 107 109 111 1 st 2 nd 3 rd 4 th 5 th 99.90 99.90 99.60 100.0 99.90 average 32 32 luminance nonlinearity (ntsc) wfm field = 2, line = 77 luminance nonlinearity (percent) mod 5 step pk-pk = 0.4 figure 130. ntsc luminance nonlinearity 1 st ?2.5 ?1.5 ?0.5 0.5 1.5 2.5 2 nd 3 rd 4 th 5 th 6 th 0.00 0.09 0.13 0.16 0.12 0.14 differential phase (degree) min = 0.00, max = 0.16, pk-pk = 0.16 1 st ?2.5 ?1.5 ?0.5 0.5 1.5 2.5 2 nd 3 rd 4 th 5 th 6 th 0.00 0.30 0.15 0.24 0.32 0.26 diifferential gain (percent) min = 0.00, max = 0.32, pk-pk = 0.32 dg dp (pal) wfm line = 570 mod 5 step average 32 32 figure 131. pal dg dp measurement 91 93 95 97 99 101 103 105 107 109 111 113 1 st 2 nd 3 rd 4 th 5 th 99.6 99.9 100.0 99.6 99.9 average 32 32 luminance nonlinearity (pal) wfm line = 570 luminance nonlinearity (percent) pk-pk = 0.8 mod 5 step figure 132. pal luminance nonlinearity
rev. b adv7190/adv7191 C66C 20ire ?10 10 0 40ire 80ire 0.5 0.0 ?0.3 chrominance amplitude error (percent) ref = 40ire packet 20ire ?5 5 0 40ire 80ire ?0.0 0.0 0.0 chrominance phase error (degree) ref = 40ire packet 20ire ?0.1 0.2 0.1 40ire 80ire 0.0 0.1 0.1 0.0 ?0.2 average 32 32 chrominance luminance intermodulation (percent of 714mv) chrominance nonlinearity(ntsc) wfm ntsc?7 combination field = 2, line = 217 figure 133. ntsc chrominance nonlinearity ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 pm noise ?82.7db rms am noise ?86.5db rms ( 0db = 714mv p - p with agc for 100% chrominance level ) db rms db rms chrominance am/pm (ntsc) wfm red field field = 2, line = 217 bandwidth 10khz to 100khz figure 134. ntsc chrominance am/pm chrominance nonlinearity(pal) wfm mod 3 step line = 572 140mv ?10 10 0 420mv 700mv 0.6 0.0 ?0.4 chrominance amplitude error (percent) ref = 420mv packet 140mv ?5 0 420mv 700mv ?0.3 0.0 ?0.3 chrominance phase error (degree) ref = 420mv packet 140mv 0.2 420mv 700mv 0.0 0.0 0.1 0.0 ?0.2 average 32 32 chrominance luminance intermodulation (percent of 700mv) figure 135. pal chrominance nonlinearity ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 pm noise ?80.5db rms am noise ?84.2db rms ( 0db = 700mv p - p with agc for 100% chrominance level ) db rms db rms chrominance am/pm (pal) wfm appropriate line = 572 bandwidth 10khz to 100khz figure 136. pal chrominance am/pm
rev. b adv7190/adv7191 C67C ?100 ?80 ?60 ?40 ?20 0 20 noise spectrum (ntsc) wfm field = 2, line = 223 amplitude (0db = 714mv p-p) 1234 56 mhz bandwidth 10khz to full pedestal noise level = ?79.7db rms figure 137. ntsc noise spectrum: pedestal ?100 ?90 ?80 ?50 ?40 ?20 0 noise spectrum (ntsc) wfm field = 2, line = 217 amplitude (0db = 714mv p-p) 1234 56 mhz bandwidth 100khz to full (tilt null) ?70 ?60 ?30 ?10 ramp noise level = ?63.1db rms figure 138. ntsc noise spectrum: ramp ?100 ?80 ?60 ?40 ?20 0 noise spectrum (pal) wfm line = 511 amplitude (0db = 714mv p-p) 123 4 57 mhz bandwidth 10khz to full 6 pedestal noise level = ?79.1db rms figure 139. pal noise spectrum: pedestal ?100 ?90 ?80 ?50 ?40 ?20 0 noise spectrum (pal) wfm line = 572 amplitude (0db = 700mv p-p) 123 4 5 7 mhz bandwidth 100khz to full (tilt null) ?70 ?60 ?30 ?10 6 noise level = ?62.3db rms ramp figure 140. pal noise spectrum: ramp
rev. b adv7190/adv7191 C68C appendix 10 vector plots apl = 39.6% sound in sync off v u yi yl g r m g cy m g cy g r 75% 100% b b system line l608 angle (deg) 0.0 gain 1.000 0.000db 625 line pal burst from source display +v and ?v figure 141. pal vector plot apl = 45.1% setup 7.5% r-y b-y yi g cy m g cy i r 75% 100% b b system line l76f1 angle (deg) 0.0 gain 1.000 0.000db 525 line ntsc burst from source q ?q ?i figure 142. ntsc vector plot
rev. b adv7190/adv7191 C69C 64-lead quad flatpack [lqfp] (st-64) top view (pins down) 1 16 17 33 32 48 49 64 0.014 (0.35) 0.031 (0.80) bsc 0.640 (16.25) 0.630 (16.00) sq 0.620 (15.75) 0.555 (14.10) 0.551 (14.00) sq 0.547 (13.90) 0.063 (1.60) max seating plane 0.004 (0.102) max lead coplanarity 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) 12 typ 10 6 2 0.007 (0.17) max 7 0 0.057 (1.45) 0.055 (1.40) 0.053 (1.35) outline dimensions dimensions shown in inches and (mm).
rev. b adv7190/adv7191 C70C revision history location page 5/02?ata sheet changed from rev. a to rev. b. added figure 46b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 changes to color bar control (mr46) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
C71C
C72C c00230C0C5/02(b) printed in u.s.a.

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